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| Keyword : VLSI
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Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k 4k@60 fps
Yiqing HUANG Takeshi IKENAGA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C
No. 3 ;
pp. 244-252
Type of Manuscript:
Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category:
Keyword:
super hi-vision, H.264/AVC, FME, VLSI, | | | Summary | Full Text:PDF | |
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Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm
Ming-Chih CHEN Shen-Fu HSIAO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12 ;
pp. 3221-3228
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
AES, VLSI, common subexpression elimination (CSE), information security, logic synthesis, | | | Summary | Full Text:PDF | |
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Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
Yanming JIA Yici CAI Xianlong HONG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12 ;
pp. 3783-3792
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
VLSI, buffer insertion, physical design, DFM, dummy fill, | | | Summary | Full Text:PDF | |
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An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor
Nobuo KARAKI Takashi NANMOTO Satoshi INOUE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C
No. 5 ;
pp. 721-730
Type of Manuscript:
Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category:
Keyword:
asynchronous circuit design, Verilog+, flexible microelectronics, LTPS TFT, SUFTLA®, VLSI, self-heating, deviation in switching delay, QDI, 4-phase handshaking, | | | Summary | Full Text:PDF | |
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High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC
Chun-Lung HSU Mean-Hom HO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A
No. 12 ;
pp. 2818-2825
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword:
VLSI, motion estimation, VBSD, H.264/AVC, | | | Summary | Full Text:PDF | |
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Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation
Ming SHAO Zhenyu LIU Satoshi GOTO Takeshi IKENAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A
No. 4 ;
pp. 756-763
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
H.264/AVC, FME, computation reusing, lossless, VLSI, | | | Summary | Full Text:PDF | |
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Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE
Hiroaki NISHIKAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C
No. 3 ;
pp. 221-229
Type of Manuscript:
INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category:
Keyword:
data-driven, multiprocessing, real-time, VLSI, | | | Summary | Full Text:PDF | |
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Rough Information Processing--A Computing Paradigm for Analog Systems--
Junichi AKITA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C
No. 11 ;
pp. 1777-1779
Type of Manuscript:
Special Section LETTER (Special Section on New System Paradigms for Integrated Electronics)
Category:
Keyword:
VLSI, analog circuit, information processing, vision chip, | | | Summary | Full Text:PDF | |
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Perspectives of Low-Power VLSI's
Takayasu SAKURAI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4 ;
pp. 429-436
Type of Manuscript:
INVITED PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
digital, memory, application, low power, VLSI, leakage, | | | Summary | Full Text:PDF | |
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A Fast Sorting VLSI Architecture for General-Purpose Standard Median Filters
Hyeongseok YU Jun-Dong CHO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A
No. 3 ;
pp. 698-700
Type of Manuscript:
Special Section LETTER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Image Processing
Keyword:
VLSI, sorting, median filter, | | | Summary | Full Text:PDF | |
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A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Kazutoshi KOBAYASHI Hidetoshi ONODERA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D
No. 3 ;
pp. 630-636
Type of Manuscript:
Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
Keyword:
simulation, test, VLSI, tester, verification, | | | Summary | Full Text:PDF | |
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Fast and Low Power Viterbi Search Engine Using Inverse Hidden Markov Model
Bo-Sung KIM Jun-Dong CHO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A
No. 3 ;
pp. 695-697
Type of Manuscript:
Special Section LETTER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword:
VLSI, HMM, Viterbi search, low-power, | | | Summary | Full Text:PDF | |
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A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem
Hyeongseok YU Byung Wook KIM Jun-Dong CHO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A
No. 3 ;
pp. 628-639
Type of Manuscript:
Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword:
decision feedback equalizer, QAM, VLSI, FIR filter, folding, | | | Summary | Full Text:PDF | |
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VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform
Pei-Yin CHEN | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/01/01
Vol. E87-A
No. 1 ;
pp. 275-279
Type of Manuscript:
LETTER
Category: VLSI Design Technology and CAD
Keyword:
VLSI, discrete wavelet transform, lifting scheme, | | | Summary | Full Text:PDF | |
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VLSI Architecture of Switching Control for AAL Type2 Switch
Masahide HATANAKA Toshihiro MASAKI Takao ONOYE Koso MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A
No. 3 ;
pp. 435-441
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
ATM, AAL type2, AAL2 switch, VLSI, | | | Summary | Full Text:PDF | |
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Unified Tag Memory Architecture with Snoop Support
Yonghwan LEE Wookyeong JEONG Yongsurk LEE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A
No. 6 ;
pp. 1172-1175
Type of Manuscript:
Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Systems and Control
Keyword:
unified tag, cache tag, TLB, VLSI, | | | Summary | Full Text:PDF | |
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An Efficient Method for The Derivation of Signal Flow Direction in Digital CMOS VLSI
Ahmed Riadh BABA-ALI Ahcene FARAH | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1902-1907
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
VLSI, CAD, MOS, switch-level, signal flow, | | | Summary | Full Text:PDF | |
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Statistical Estimation of CMOS Circuit Activity under Probabilistic Delays
Tan-Li CHOU Kaushik ROY | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A
No. 10 ;
pp. 1915-1923
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
VLSI, statistical power estimation, | | | Summary | Full Text:PDF | |
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A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays
Hiroshi SHIROTA Satoshi SHIBATANI Masayuki TERAI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A
No. 3 ;
pp. 506-513
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
multilayer routing, layout, CAD, VLSI, | | | Summary | Full Text:PDF | |
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Systolic Realization of Cyclic Wavelet Transforms and Cyclic Wavelet Packet Transforms
J. W. WANG C. H. CHEN | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/08/25
Vol. E79-A
No. 8 ;
pp. 1240-1242
Type of Manuscript:
Special Section LETTER (Special Section on Digital Signal Processing)
Category:
Keyword:
cyclic wavelet transforms, cyclic wavelet packet transforms, VLSI, | | | Summary | Full Text:PDF | |
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A Hybrid Hierarchical Global Router for Multi-Layer VLSI's
Masayuki HAYASHI Shuji TSUKIYAMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A
No. 3 ;
pp. 337-344
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword:
hybrid hierarchical router, global routing, multi-layer routing, CAD, VLSI, | | | Summary | Full Text:PDF | |
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Research Topics and Results on Simulation for VLSI
Isao SHIRAKAWA Nagisa ISHIURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A
No. 7 ;
pp. 1070-1076
Type of Manuscript:
Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)
Category:
Keyword:
VLSI, circuit simulation, logic simulation, | | | Summary | Full Text:PDF | |
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A Recycling Scheme for Layout Patterns Used in an Old Fabrication Technology
Yuji SHIGEHIRO Isao SHIRAKAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A
No. 6 ;
pp. 886-893
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Algorithms for VLSI Design
Keyword:
VLSI, fabrication technology, mask pattern, layout description, | | | Summary | Full Text:PDF | |
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Timing Driven Placement Based on Fuzzy Theory
Ze Cang GU Shoichiro YAMADA Shojiro YONEDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A
No. 7 ;
pp. 917-919
Type of Manuscript:
Special Section LETTER (Special Section on the 1992 IEICE Spring Conference)
Category:
Keyword:
fuzzy, timing, placement, VLSI, | | | Summary | Full Text:PDF | |
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