Keyword : VLSI layout

Timing-Driven Global Routing with Efficient Buffer Insertion
Jingyu XU Xianlong HONG Tong JING 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11 ; pp. 3188-3195
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI layout, global routing, timing-driven, buffer insertion, routability, 
 Summary | Full Text:PDF
VLSI Layout of Trees into Grids of Minimum Width
Akira MATSUBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A  No. 5 ; pp. 1059-1069
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
VLSI layout, graph layout, graph embedding, grid, aspect ratio, 
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On the Complexity of Minimum Congestion Embedding of Acyclic Graphs into Ladders
Akira MATSUBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5 ; pp. 1218-1226
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph embedding, graph layout, VLSI layout, grid, 
 Summary | Full Text:PDF
The Complexity of Embedding of Acyclic Graphs into Grids with Minimum Congestion
Akira MATSUBAYASHI Masaya YOKOTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/11/25
Vol. E83-A  No. 11 ; pp. 2390-2394
Type of Manuscript:  LETTER
Category: Graphs and Networks
Keyword: 
graph embedding, graph layout, VLSI layout, grid, 
 Summary | Full Text:PDF
Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees
Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5 ; pp. 767-774
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithm, minimum cut linear arrangement, VLSI layout, adder tree, multiplier, 
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Cost-Radius Balanced Spanning/Steiner Trees
Hideki MITSUBAYASHI Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4 ; pp. 689-694
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
delay, spanning tree, steiner tree, VLSI layout, 
 Summary | Full Text:PDF
On the Complexity of Embedding of Graphs into Grids with Minimum Congestion
Akira MATSUBAYASHI Shuichi UENO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/04/25
Vol. E79-A  No. 4 ; pp. 469-476
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
NP-completeness, graph embedding, congestion, grid, VLSI layout, 
 Summary | Full Text:PDF
Minimal Forbidden Minors for the Family of Graphs with Proper-Path-Width at Most Two
Atsushi TAKAHASHI Shuichi UENO Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1828-1839
Type of Manuscript:  PAPER
Category: Graphs and Networks
Keyword: 
proper-path-width, path-width, minor-closed family, minimal forbidden minor, VLSI layout, 
 Summary | Full Text:PDF