Keyword : VLSI design


Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems
Jaeyong CHUNG Woochul KANG 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11 ; pp. 1073-1076
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
neuromorphic systemsVLSI designcomputer-aided design
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Achieving Maximum Performance for Bus-Invert Coding with Time-Splitting Transmitter Circuit
Myungchul YOON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2357-2363
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
low-power designVLSI designbus-invert codingperformance analysis
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Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders
Ming-Der SHIEH Shih-Hao FANG Shing-Chung TANG Der-Wei YANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 549-557
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
error control codinglow-density parity-check (LDPC) codesquasi-cyclic (QC) LDPC codespartially parallel architectureVLSI design
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Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)
Su-Hon LIN Ming-Hwa SHEU Chao-Hsiang WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/07/01
Vol. E91-D  No. 7 ; pp. 2058-2060
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
residue number system (RNS)residue-to-binary convertermoduli setVLSI design
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A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
Jianping HU Tiefeng XU Hong LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1479-1485
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
register filelow poweradiabatic logicVLSI design
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Boundary Scan Test Scheme for IP Core Identification via Watermarking
Yu-Cheng FAN Hen-Wai TSAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1397-1400
Type of Manuscript:  Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
boundary scan test scheme (BSTS)intellectual property (IP) identificationsystem on a chip (SOC)VLSI designwatermarking
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A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG Chien-Jyh LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3109-3115
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
low-powerarchitectureVLSI designFSMgatingsynthesis
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Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme
Yeu-Horng SHIAU Jer Min JOU Chin-Chi LIU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/07/01
Vol. E87-D  No. 7 ; pp. 1867-1877
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
discrete wavelet transformVLSI designpipelining architecturemultimedia applications
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A High-Performance Tree-Block Pipelining Architecture for Separable 2-D Inverse Discrete Wavelet Transform
Yeu-Horng SHIAU Jer Min JOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10 ; pp. 1966-1975
Type of Manuscript:  Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
inverse discrete wavelet transformVLSI designpipelining architecturemultimedia applications
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VLSI Implementation of Lifting Discrete Wavelet Transform Using the 5/3 Filter
Pei-Yin CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/12/01
Vol. E85-D  No. 12 ; pp. 1893-1897
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
discrete wavelet transformlifting schemeVLSI designmultimedia applications
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Efficient Timing Verification of Latch-Synchronized Systems
Sang-Yeol HAN Young Hwan KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/09/25
Vol. E80-A  No. 9 ; pp. 1676-1683
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI designsynchronous elementscritical path analysistiming error
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High-Level Synthesis --A Tutorial
Allen C.-H. WU Youn-Long LIN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 209-218
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high-level synthesisdesign methodologyVLSI designdesign automation
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Wire Length Expressions for Analytical Placement Approach
Shoichiro YAMADA Masahiro KASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4 ; pp. 716-718
Type of Manuscript:  LETTER
Category: Computer Aided Design (CAD)
Keyword: 
placementCADVLSI design
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An Automated Approach to Generating Leaf Cells for a Macro Cell Configuration
Ritsu KUSABA Hiroshi MIYASHITA Takumi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/08/25
Vol. E76-A  No. 8 ; pp. 1334-1342
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
VLSI designcomputer aided designmacro cell
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