Keyword : VLSI array processor


A Systematic Design of Fault Tolerant Systolic Arrays Based on Triple Modular Redundancy in Time-Processor Space
Mineo KANEKO Hiroyuki MIYAUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/12/25
Vol. E79-D  No. 12 ; pp. 1676-1689
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
VLSI array processorsystolic arrayfault tolerancecommunication linkdependence graph
 Summary | Full Text:PDF(1.1MB)