Keyword : VLSI architecture


Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing
Jianbin ZHOU Dajiang ZHOU Takeshi YOSHIMURA Satoshi GOTO 
Publication:   
Publication Date: 2018/04/01
Vol. E101-C  No. 4 ; pp. 263-272
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
compressed sensingapproximate DCTmeasurement codingmeasurement matrixintra predictionVLSI architectureCMOS image sensor
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High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder
Jianbin ZHOU Dajiang ZHOU Shihao WANG Takeshi YOSHIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2519-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
HEVC/H.265 decoderintra predictionVLSI architecture8K UHDTV
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VLSI Implementation of an Interference Canceller Using Dual-Frame Processing for OFDM-IDMA Systems
Shingo YOSHIZAWA Mai NOZAKI Hiroshi TANIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/03/01
Vol. E98-A  No. 3 ; pp. 811-819
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
OFDM-IDMAinterference cancellerVLSI architecture
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A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
Kazuhiro NAKAMURA Ryo SHIMAZAKI Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 456-467
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architectureisolated word recognition
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Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems
Shingo YOSHIZAWA Yoshikazu MIYANAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2 ; pp. 550-558
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
pipeline FFT processorMIMO-OFDMVLSI architectureIEEE 802.11ac
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VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
Hiroki NOGUCHI Kazuo MIURA Tsuyoshi FUJINAGA Takanobu SUGAHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 458-467
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architecture
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Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
Tianruo ZHANG Chen LIU Minghui WANG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 401-410
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
H.264 encodingVLSI architectureregion-of-interestlow power
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A General Reverse Converter Architecture with Low Complexity and High Performance
Keivan NAVI Mohammad ESMAEILDOUST Amir SABBAGH MOLAHOSSEINI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2 ; pp. 264-273
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
residue arithmeticreverse converterresidue number system (RNS)VLSI architecture
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A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
Kazuhiro NAKAMURA Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/02/01
Vol. E93-D  No. 2 ; pp. 300-305
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
speech recognitionhidden Markov model (HMM)VLSI architecture
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High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders
Kyo TAKAHASHI Shingo SATO Tadamichi KUDO Yoshitaka TSUNEKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2 ; pp. 633-637
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
adaptive filtercut-set retiming4-2AdderVLSI architecture
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High Throughput VLSI Architecture of a Fast Mode Decision Algorithm for H.264/AVC Intra Encoding
Tianruo ZHANG Guifen TIAN Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3630-3637
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
H.264/AVCintra predictionfast mode decision algorithmVLSI architecture
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Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders
Ming-Der SHIEH Tai-Ping WANG Chien-Ming WU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/09/01
Vol. E91-D  No. 9 ; pp. 2300-2311
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
Viterbi decoder (VD)in-place schedulingpath metric memory managementVLSI architecture
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A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC
Zhenyu LIU Yang SONG Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/12/01
Vol. E89-C  No. 12 ; pp. 1928-1936
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
H.264AVCvariable block size motion estimationVLSI architecture
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Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator
Shingo YOSHIZAWA Yoshikazu MIYANAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/10/01
Vol. E89-A  No. 10 ; pp. 2866-2873
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
wireless communicationvariable wordlengthVLSI architectureOFDM
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Efficient DSP Architecture for Viterbi Decoding with Small Trace Back Latency
Weon Heum PARK Myung Hoon SUNWOO Seong Keun OH 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/10/01
Vol. E89-B  No. 10 ; pp. 2813-2818
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
Viterbi algorithmDSPtrace backinstructionVLSI architecturewireless communication
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Design Method for 2-Channel Signal Word Decomposed Filters with Minimum Output Error and Their Effective VLSI Implementation
Kouhei HOSOKAWA Mitsuhiko YAGYU Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/08/01
Vol. E88-A  No. 8 ; pp. 2044-2054
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from the 19th Symposium on Signal Processing)
Category: Digital Signal Processing
Keyword: 
signal word decomposed filtersVLSI architecturetransistor count
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Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000
Amit Kumar GUPTA Saeid NOOSHABADI David TAUBMAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8 ; pp. 1878-1884
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 2)
Category: Image Processing and Multimedia Systems
Keyword: 
JPEG2000concurrent symbol processingbit plane coderVLSI architecture
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Complex Hadamard Transforms: Properties, Relations and Architecture
Bogdan J. FALKOWSKI Susanto RAHARDJA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8 ; pp. 2077-2083
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
complex Hadamard transformdiscrete transformsVLSI architecture
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A New Implementation Technique to Decode the Convolutional Code in Trellis-Coded Modulation
Anh DINH Xiao HU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 619-627
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
TCMlook-up-tableViterbi decodingIP coreASICVLSI architecture
 Summary | Full Text:PDF

A Cost-Effective CORDIC-Based Architecture for Adaptive Lattice Filters
Shin'ichi SHIRAISHI Miki HASEYAMA Hideo KITAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 567-576
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Audio/Speech Coding
Keyword: 
adaptive filtergradient adaptive latticeCORDICVLSI architecture
 Summary | Full Text:PDF

Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 399-409
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion estimationlow bit resolutionVLSI architectureparallelismlow power
 Summary | Full Text:PDF

VLSI Architecture for Real-Time Fractal Image Coding Processors
Hideki YAMAUCHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A  No. 3 ; pp. 452-458
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
VLSI architectureimage codingfractal compression
 Summary | Full Text:PDF

A Novel Computationally Adaptive Hardware Algorithm for Video Motion Estimation
Vasily G. MOSHNYAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1749-1754
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Imaging Circuits and Algorithms
Keyword: 
video processingmotion estimationhardware algorithmVLSI architecture
 Summary | Full Text:PDF

An Overview of Video Coding VLSIs
Ryota KASAI Toshihiro MINAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1920-1929
Type of Manuscript:  INVITED PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processors
Keyword: 
video compression/decompressionVLSI architecturevideo signal processorbuilding block approachlow-power technology
 Summary | Full Text:PDF

Design of a Multiplier-Accumulator for High Speed lmage Filtering
Farhad Fuad ISLAM Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/11/25
Vol. E76-A  No. 11 ; pp. 2022-2032
Type of Manuscript:  PAPER
Category: VLSI Design Technology
Keyword: 
binary multiplier-accumulatorthroughputimage filteringVLSI architecture
 Summary | Full Text:PDF

An Architecture for High Speed Array Multiplier
Farhad Fuad ISLAM Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/08/25
Vol. E76-A  No. 8 ; pp. 1326-1333
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary multiplicationarray multiplerVLSI architecture
 Summary | Full Text:PDF