Keyword : VLSI CAD


EQ-Sequences for Coding Floorplans
Hua-An ZHAO Chen LIU Yoji KAJITANI Keishi SAKANUSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3233-3243
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan
Keyword: 
floorplanplacementVLSI CADQ-sequence
 Summary | Full Text:PDF(800KB)

A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths
Susumu KOBAYASHI Masato EDAHIRO Mikio KUBO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2499-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSI CADscan-chainlayout designdesign for testability
 Summary | Full Text:PDF(736.9KB)

Power and Area Minimization by Reorganizing CMOS Complex-Gates
Masayoshi TACHIBANA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 312-320
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
VLSI CADlogic synthesiscomplex-gatetransistor sizing
 Summary | Full Text:PDF(798.2KB)

An Integer Programming Approach to Instruction Set Selection Problem
Alauddin Y. ALOMARY Masaharu IMAI Jun SATO Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1849-1857
Type of Manuscript:  PAPER
Category: VLSI Design Technology
Keyword: 
ASIPVLSI CADinstruction set optimizationbranch-and-bound method
 Summary | Full Text:PDF(745.3KB)

A Hierarchical Multi-Layer Global Router
Masayuki HAYASHI Hiroyoshi YAMAZAKI Shuji TSUKIYAMA Nobuyuki NISHIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1294-1300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
global routerlayeringhierarchical routermultilayer VLSIVLSI CAD
 Summary | Full Text:PDF(606.9KB)