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Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters
Takashi MIYAMORI Hui XU Hiroyuki USUI Soichiro HOSODA Toru SANO Kazumasa YAMAMOTO Takeshi KODAKA Nobuhiro NONOGAKI Nau OZAKI Jun TANABE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C
No. 4 ;
pp. 360-368
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
many-core, network-on-chip, VLIW, low power, face detection, H.264, super resolution, | | | Summary | Full Text:PDF | |
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Unified Phase Compiler by Use of 3-D Representation Space
Takefumi MIYOSHI Nobuhiko SUGINO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A
No. 4 ;
pp. 838-845
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
optimized compiler, VLIW, DSP, algorithm, | | | Summary | Full Text:PDF | |
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