Keyword : VLIW


Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters
Takashi MIYAMORI Hui XU Hiroyuki USUI Soichiro HOSODA Toru SANO Kazumasa YAMAMOTO Takeshi KODAKA Nobuhiro NONOGAKI Nau OZAKI Jun TANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 360-368
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
many-corenetwork-on-chipVLIWlow powerface detectionH.264super resolution
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Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core
Takahiro KUMURA Norio KAYAMA Shinichi SHIONOYA Kazuo KUMAGIRI Takao KUSANO Makoto YOSHIDA Masao IKEKAWA Ichiro KURODA Takao NISHITANI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6 ; pp. 1224-1230
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
MPEG-4DSPVLIWlow-power
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Unified Phase Compiler by Use of 3-D Representation Space
Takefumi MIYOSHI Nobuhiko SUGINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 838-845
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
optimized compilerVLIWDSPalgorithm
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A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 552-558
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
parallel processingVLIWSMTlow powernanometerleakage power
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ODiN: A 32-Bit High Performance VLIW DSP for Software Defined Radio Applications
Seung Eun LEE Yong Mu JEONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1780-1786
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
DSP (Digital Signal Processor)SDR (Software Defined Radio)VLIWVLSI
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VLaTTe: A Java Just-in-Time Compiler for VLIW with Fast Scheduling and Register Allocation
Suhyun KIM Soo-Mook MOON Kemal EBCIOLU Erik ALTMAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/07/01
Vol. E87-D  No. 7 ; pp. 1712-1720
Type of Manuscript:  Special Section PAPER (Special Section on Hardware/Software Support for High Performance Scientific and Engineering Computing)
Category: Software Support and Optimization Techniques
Keyword: 
Java virtual machinejust-in-time compilationVLIWschedulingregister allocation
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A 12.8 GOPS/2.1GFLOPS 8-Way VLIW Embedded Processor with Advanced Multimedia Mechanism
Yasuki NAKAMURA Hiroshi OKANO Atsuhiro SUGA Hiromasa TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 529-534
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: 
Keyword: 
VLIWmicroprocessormultimedia
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A 4GOPS 3 Way-VLIW Image Recognition Processor Based on a Configurable Media Processor
Hiroyuki TAKANO Takashi MIYAMORI Yasuhiro TANIGUCHI Yoshihisa KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 347-351
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Product Designs
Keyword: 
configurable media-processorVLIWimage-recognition LSI
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Novel VLIW Code Compaction Method for a 3D Geometry Processor
Hiroaki SUZUKI Hiroyuki KAWAI Hiroshi MAKINO Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2885-2893
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
VLIWcode compactionASSP3D geometry processorcomputer graphics
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A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores
Jeong-Min KIM Yun-Su SHIN In-Gu HWANG Kwang-Sun LEE Sang-Il HAN Sang-Gyu PARK Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 183-192
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLIWmedia processorvideophone
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A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor
Hiroshi OKANO Atsuhiro SUGA Hideo MIYAKE Yoshimasa TAKEBE Yasuki NAKAMURA Hiromasa TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 150-156
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLIWmicroprocessormultimediaSIMDsynthesis
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A Dual-Issue RISC Processor for Multimedia Signal Processing
Hisakazu SATO Toyohiko YOSHIDA Masahito MATSUO Toru KENGAKU Koji TSUCHIHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1374-1381
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
multimediaDSPmicroprocessorVLIW
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A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor
Akira YAMADA Toyohiko YOSHIDA Tetsuya MATSUMURA Shin-ichi URAMOTO Koji TSUCHIHASHI Edgar HOLMANN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1382-1390
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
multimedia processormedia processorVLIWMPEGmicroprocessor
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A VLIW Geometry Processor with Software Bypass Mechanism
Yasunori KIMURA Akira ASATO Toshihiro OZAWA Hiroshi NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 669-679
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
3D graphicsgeometry processingVLIWcompiler
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A 2 V 250 MHz VLIW Multimedia Processor
Toyohiko YOSHIDA Akira YAMADA Edgar HOLMANN Hidehiro TAKATA Atsushi MOHRI Yukihiko SHIMAZU Kiyoshi NAKAKIMURA Keiichi HIGASHITANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 651-660
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
multimedia processormedia processorVLIWMPEGAC-3microprocessor
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Future Directions of Media Processors
Shunichi ISHIWATA Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 629-635
Type of Manuscript:  INVITED PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: Multimedia
Keyword: 
media processorVLIWmultimedia extensionwide memory bandwidthlow power consumption
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Speculative Execution and Reducing Branch Penalty on a Superscalar Processor
Hideki ANDO Chikako NAKANISHI Hirohisa MACHIDA Tetsuya HARA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1080-1093
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
superscalarVLIWspeculative execution
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