IEICE SEARCH SYSTEM

Keyword : VHDL

VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks David ALEDO Benjamin CARRION SCHAFER Félix MORENO
Publication: Publication Date: 2019/03/01 Vol. E102-D No. 3 ; pp. 512-521 Type of Manuscript: PAPER Category: Computer System Keyword: VHDL, SystemC, high-level synthesis (HLS), artificial neural network (ANN),
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HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits Jung-Lin YANG Jau-Cheng WEI Shin-Nung LU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2590-2599 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: asynchronous, burst-mode, extended burst-mode, HDL, handshake package, VHDL, Verilog, self-timed,
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A Flexible Architecture for Digital Signal Processing Wichai BOONKUMKLAO Yoshikazu MIYANAGA Kobchai DEJHAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 ; pp. 2179-2186 Type of Manuscript: PAPER Category: VLSI Systems Keyword: FRM, PCA, reconfigurable architecture, IP, VHDL,
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An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation Jinku CHOI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2603-2611 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: motion estimation, block-matching, algorithm, architecture, VHDL,
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A Study on the Design of VME System Controller Kang Hyeon RHEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/25 Vol. E83-A No. 6 ; pp. 1083-1090 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: factory automaton, VME system controller, VHDL, FPGA,
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Hardware Synthesis from C Programs with Estimation of Bit Length of Variables Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 ; pp. 2338-2346 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, hardware/software codesign, VHDL, C language, compiler,
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A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy Milan VASILKO David CABANIS
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 ; pp. 2465-2474 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic simulation, Dynamically Reconfigurable Logic, run-time reconfiguration, VHDL, FPGAs,
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Program Slicing on VHDL Descriptions and Its Evaluation Shigeru ICHINOSE Mizuho IWAIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 ; pp. 2585-2594 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Design Reuse Keyword: hardware description language, VHDL, program slicing, design reuse, component extraction,
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Combining Architectural Simulation and Behavioral Synthesis Abderrazak JEMAI Polen KISSION Ahmed Amine JERRAYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 ; pp. 1756-1766 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: architectural simulation, behavioral synthesis, VHDL,
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High-Level Modeling and Synthesis of Communicating Processes Using VHDL Wayne WOLF Richard MANNO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/25 Vol. E76-D No. 9 ; pp. 1039-1046 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: High-Level Design Keyword: high-level synthesis, VHDL, control-dominated systems,
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Integrated Design and Test Assistance for Pipeline Controllers Hiroaki IWASHITA Tsuneo NAKATA Fumiyasu HIROSE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-D No. 7 ; pp. 747-754 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: design verification, test program, VHDL, RISC processor,
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Functional Design of a Special Purpose Processor Based on High Level Specification Description Hironobu KITABATAKE Katsuhiko SHIRAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 ; pp. 1182-1190 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, ASIC design, VHDL,
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New Trend and Future Issues of Hardware Description Language and High-Level Synthesis Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/03/25 Vol. E75-A No. 3 ; pp. 307-313 Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: HDL, high-level synthesis, VHDL, verilog HDL, UDL/I, PARTHENON, SFL,
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