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A Low-Jitter Injection-Locked Clock Multiplier Using 97-µW Transformer-Based VCO with 18-kHz Flicker Noise Corner
Zheng SUN Hanli LIU Dingxin XU Hongye HUANG Bangan LIU Zheng LI Jian PANG Teruki SOMEYA Atsushi SHIRANE Kenichi OKADA | Publication:
Publication Date: 2021/07/01
Vol. E104-C
No. 7 ;
pp. 289-299
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
injection lock, frequency multiplier, IoT, ultra-low power, VCO, transformer, FoM, flicker noise, CMOS, | | | Summary | Full Text:PDF | |
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A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology
Yu HOU Zhijie CHEN Masaya MIYAHARA Akira MATSUZAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A
No. 12 ;
pp. 2473-2482
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
Op-amp free, SAR, VCO, hybrid, 1-1 MASH ADC, | | | Summary | Full Text:PDF | |
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A Triple-Push Voltage Controlled Oscillator in 0.13-µm RFCMOS Technology Operating Near 177GHz
Namhyung KIM Kyungmin KIM Jae-Sung RIEH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2014/05/01
Vol. E97-C
No. 5 ;
pp. 444-447
Type of Manuscript:
BRIEF PAPER
Category:
Keyword:
VCO, triple-push, phase noise, | | | Summary | Full Text:PDF | |
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A 28-GHz, -187.4-dBc/Hz-FOMT Low-Phase-Noise CMOS VCO Using an Amplitude-Redistribution Technique
Yusuke WACHI Toshiyuki NAGASAKU Hiroshi KONDOH | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Vol. E95-C
No. 6 ;
pp. 1042-1049
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
millimeter-wave, CMOS, VCO, phase-noise, | | | Summary | Full Text:PDF | |
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A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider
Shoichi HARA Kenichi OKADA Akira MATSUZAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C
No. 6 ;
pp. 763-769
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
CMOS, VCO, divider, inductor, | | | Summary | Full Text:PDF | |
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The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique
Shoichi HARA Rui MURAKAMI Kenichi OKADA Akira MATSUZAWA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Vol. E93-A
No. 2 ;
pp. 424-430
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
CMOS, VCO, divider, inductor, | | | Summary | Full Text:PDF | |
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Low Phase Noise, InGaP/GaAs HBT VCO MMIC for Millimeter-Wave Applications
Satoshi KURACHI Toshihiko YOSHIMASU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C
No. 4 ;
pp. 678-682
Type of Manuscript:
Special Section PAPER (Special Section on Fundamental and Application of Advanced Semiconductor Devices)
Category: Compound Semiconductor Devices
Keyword:
InGaP/GaAs HBT, VCO, millimeter-wave, low phase noise, | | | Summary | Full Text:PDF | |
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A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6 ;
pp. 956-963
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, | | | Summary | Full Text:PDF | |
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High-Speed Wide-Locking Range VCO with Frequency Calibration
Takeo YASUDA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2616-2622
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
Keyword:
VCO, PLL, high speed, wide locking range, calibration, | | | Summary | Full Text:PDF | |
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A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm
Hyuk-Jun SUNG Kwang Sub YOON | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/02/25
Vol. E83-A
No. 2 ;
pp. 267-271
Type of Manuscript:
Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
dual-looped PLL, PFD, VCO, V-I converter, current-pumping algorithm, | | | Summary | Full Text:PDF | |
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A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C
No. 7 ;
pp. 1334-1340
Type of Manuscript:
PAPER
Category: Integrated Electronics
Keyword:
PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, | | | Summary | Full Text:PDF | |
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A Novel Broad-Band MMIC VCO Using an Active Inductor
Hitoshi HAYASHI Masahiro MURAGUCHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A
No. 2 ;
pp. 224-229
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category:
Keyword:
MMIC, broad-band, inductor, active, VCO, | | | Summary | Full Text:PDF | |
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A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C
No. 12 ;
pp. 1951-1956
Type of Manuscript:
Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword:
electronic circuits, clock generator, PLL, frequency multiplication, VCO, VCO gain, jitter, pull-in range, CMOS, VSP, | | | Summary | Full Text:PDF | |
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A Study of a MOS VCO Circuit by Using a Current–Controlled Differential Delay Cell
Yasuhiro SUGIMOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A
No. 11 ;
pp. 1929-1931
Type of Manuscript:
Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category:
Keyword:
MOS analog circuit, PLL, VCO, current control, differential delay cell, | | | Summary | Full Text:PDF | |
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