Keyword : TMR


Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures
Takashi IMAGAWA Masayuki HIROMOTO Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2524-2532
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
soft errorTMRreliabilitymethodology
 Summary | Full Text:PDF(653KB)

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
Jun FURUTA Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 340-346
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
TMRbuilt-in soft errorSEUSET
 Summary | Full Text:PDF(385.2KB)