IEICE Trans

Keyword : SRAM

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 ; pp. 1741-1750 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: standard-cell memory, SRAM, near-threshold computing, cache memory, system-on-chip,
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Development of a Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply Nobuaki KOBAYASHI Tadayoshi ENOMOTO
Publication: Publication Date: 2018/10/01 Vol. E101-C No. 10 ; pp. 822-830 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: CMOS, SRAM, static-noise margin, standby power dissipation, leakage current, Self-controllable Voltage Level (SVL) circuit,
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Applying Razor Flip-Flops to SRAM Read Circuits Ushio JIMBO Junji YAMADA Ryota SHIOYA Masahiro GOSHIMA
Publication: Publication Date: 2017/03/01 Vol. E100-C No. 3 ; pp. 245-258 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: random variation, timing fault detection and recovery, dynamic voltage and frequency scaling (DVFS), SRAM,
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Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method Sangheon OH Changhwan SHIN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/05/01 Vol. E99-C No. 5 ; pp. 541-543 Type of Manuscript: BRIEF PAPER Category: Keyword: random variation, FinFET, SRAM, worst-case sampling,
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A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals Yoshifumi KAWAMURA Naoya OKADA Yoshio MATSUDA Tetsuya MATSUMURA Hiroshi MAKINO Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/05/01 Vol. E99-A No. 5 ; pp. 917-928 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, MCU peripherals, field programmable devices, sequencer, SRAM,
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A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme Nobutaro SHIBATA Takako ISHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/02/01 Vol. E99-C No. 2 ; pp. 316-330 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 4-way set-associative, cache-tag, CMOS, directed graph, dual-rail wordline, FD-SOI, I/O-separated memory cell, LRU, NRZ-type write-enable signal, SIMOX, SRAM,
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A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC Heming SUN Dajiang ZHOU Peilin LIU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2467-2476 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: HEVC, IDCT, SRAM, area-efficient, video coding,
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Single-Grain Si Thin-Film Transistors for Monolithic 3D-ICs and Flexible Electronics Ryoichi ISHIHARA Jin ZHANG Miki TRIFUNOVIC Jaber DERAKHSHANDEH Negin GOLSHANI Daniel M. R. TAJARI MOFRAD Tao CHEN Kees BEENAKKER Tatsuya SHIMODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 ; pp. 227-237 Type of Manuscript: INVITED PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: silicon, thin-film transistor, 3D-ICs, excimer-laser, crystallization, SRAM, image sensor, flexible electronics,
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Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis Shiho HAGIWARA Takanori DATE Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 ; pp. 280-288 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: design for manufacturing, Monte Carlo method, importance sampling, SRAM, process variation, yield, norm minimization, Gaussian mixture models, clustering, hypersphere sampling,
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A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs Song JIA Heqing XU Fengfeng WU Yuan WANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/09/01 Vol. E96-C No. 9 ; pp. 1205-1207 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: SRAM, sense amplifier, winner-take-all, high speed,
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Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout Shusuke YOSHIMOTO Shunsuke OKUMURA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/07/01 Vol. E96-A No. 7 ; pp. 1579-1585 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: SRAM, soft error rate (SER), multiple cell upset (MCU), neutron particle, twin well, triple well,
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NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM Nurul Ezaila ALIAS Anil KUMAR Takuya SARAYA Shinji MIYANO Toshiro HIRAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/05/01 Vol. E96-C No. 5 ; pp. 620-623 Type of Manuscript: BRIEF PAPER Category: Keyword: Negative Bias Temperature Instability (NBTI), variability, SRAM, transistor, MOSFET,
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A High Performance Current Latch Sense Amplifier with Vertical MOSFET Hyoungjun NA Tetsuo ENDOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/05/01 Vol. E96-C No. 5 ; pp. 655-662 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: current latch sense amplifier, vertical MOSFET, SRAM, sensing time, speed, current, voltage gain, stability, yield, circuit area,
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Independent-Double-Gate FinFET SRAM Technology Kazuhiko ENDO Shin-ichi OUCHI Takashi MATSUKAWA Yongxun LIU Meishoku MASAHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 ; pp. 413-423 Type of Manuscript: INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: multi-gate devices, FinFET, SRAM, noise margin,
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A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells Shunsuke OKUMURA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2226-2233 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: SRAM, chip ID, physical unclonable function (PUF),
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Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/10/01 Vol. E95-C No. 10 ; pp. 1675-1681 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SRAM, soft error, multiple-bit upset (MBU), single-event upset (SEU), error correction coding (ECC), alpha particle, neutron particle,
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Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Koji NII Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 ; pp. 1359-1365 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: SRAM, single-event upset (SEU), bit error rate (BER), soft error rate (SER), neutron particle, alpha particle,
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A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme Shunsuke OKUMURA Hidehiro FUJIWARA Kosuke YAMAGUCHI Shusuke YOSHIMOTO Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 579-585 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, FD-SOI, Inter-die variation,
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A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke YOSHIMOTO Masaharu TERADA Shunsuke OKUMURA Toshikazu SUZUKI Shinji MIYANO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 572-578 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, 8T, low energy, disturb, half select, write back,
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Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation Takuya SAWADA Taku TOSHIKAWA Kumpei YOSHIKAWA Hidehiro TAKATA Koji NII Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 586-593 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: SRAM, Immunity, On chip monitoring, Built-in self testing,
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Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes Takashi MATSUDA Shintaro IZUMI Yasuharu SAKAI Takashi TAKEUCHI Hidehiro FUJIWARA Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/01/01 Vol. E95-B No. 1 ; pp. 178-188 Type of Manuscript: PAPER Category: Network Keyword: wireless sensor network, data aggregation, data storage management, SRAM,
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Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier Jinn-Shyan WANG Pei-Yao CHANG Chi-Chang LIN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/01/01 Vol. E95-C No. 1 ; pp. 172-175 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: SRAM, subthreshold, variations,
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A Self-Timed SRAM Design for Average-Case Performance Je-Hoon LEE Young-Jun SONG Sang-Choon KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/08/01 Vol. E94-D No. 8 ; pp. 1547-1556 Type of Manuscript: PAPER Category: Computer System Keyword: asynchronous circuit, SRAM, self-timed logic, memory segmentation,
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Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit Kei MATSUMOTO Tetsuya HIROSE Yuji OSAKI Nobutaka KUROKI Masahiro NUMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 ; pp. 1042-1048 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: SRAM, threshold voltage variation, compensation circuit, process variation, temperature variation, PVT variation,
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A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM Tadayoshi ENOMOTO Nobuaki KOBAYASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 530-538 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: SRAM, leakage power, “write” margin, “read” margin,
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Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI Yuji KUNITAKE Toshinori SATO Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 520-529 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: NBTI, SRAM, static noise margin, stress probability, register file, cache memory,
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Adaptive Circuits for the 0.5-V Nanoscale CMOS Era Kiyoo ITOH Masanao YAMAOKA Takashi OSHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 ; pp. 216-233 Type of Manuscript: INVITED PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: minimum operating voltage, SRAM, DRAM, FD-SOI, FinFET,
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An Efficient Fault Syndromes Simulator for SRAM Memories Wan Zuha WAN HASAN Izhal ABD HALIN Roslina MOHD SIDEK Masuri OTHMAN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/05/01 Vol. E92-C No. 5 ; pp. 639-646 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: testing, diagnosis, coupling faults, stuck-at faults March test algorithm, built-in self-test (BIST), built-in self-diagnosis (BISD), automated march-based test algorithm, SRAM,
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A Dependable SRAM with 7T/14T Memory Cells Hidehiro FUJIWARA Shunsuke OKUMURA Yusuke IGUCHI Hiroki NOGUCHI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 ; pp. 423-432 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: SRAM, dependability, quality of a bit,
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Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration Hirofumi SHINOHARA Koji NII Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 ; pp. 1488-1500 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SRAM, memory cell, static noise margin, SNM, variability,
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A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology Masako FUJII Koji NII Hiroshi MAKINO Shigeki OHBAYASHI Motoshige IGARASHI Takeshi KAWAMURA Miho YOKOTA Nobuhiro TSUDA Tomoaki YOSHIZAWA Toshikazu TSUTSUI Naohiko TAKESHITA Naofumi MURATA Tomohiro TANAKA Takanari FUJIWARA Kyoko ASAHINA Masakazu OKADA Kazuo TOMITA Masahiko TAKEUCHI Shigehisa YAMAMOTO Hiromitsu SUGIMOTO Hirofumi SHINOHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/08/01 Vol. E91-C No. 8 ; pp. 1338-1347 Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures (ICMTS2007)) Category: Keyword: large-scale integration, logic circuit fault diagnosis, SRAM, yield optimization,
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A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer Yuichiro MURACHI Junichi MIYAKOSHI Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Fang YIN Jangchung LEE Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 465-478 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: low power, motion estimation, H.264, systolic array, MBAFF, SRAM,
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Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 410-417 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: single event upset, SRAM, DRAM, reliability, cache architecture, task scheduling,
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FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction Shin-ichi O'UCHI Meishoku MASAHARA Kazuhiko ENDO Yongxun LIU Takashi MATSUKAWA Kunihiro SAKAMOTO Toshihiro SEKIGAWA Hanpei KOIKE Eiichi SUZUKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 534-542 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: SRAM, FinFET, 4T-FinFET, standby power, dynamic threshold-voltage control,
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Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM Masaaki IIJIMA Kayoko SETO Masahiro NUMA Akira TADA Takashi IPPOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 ; pp. 2691-2694 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Memory Design and Test Keyword: PD-SOI, body-bias, SRAM, low power design,
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4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words Koh JOHGUCHI Hans Jurgen MATTAUSCH Tetsushi KOIDE Tetsuo HIRONAKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/11/01 Vol. E90-C No. 11 ; pp. 2157-2160 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: multi-port memory, unified cache, SRAM, CMOS,
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A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 749-757 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: SRAM, 1R/1W-SRAM, disturbed access, SNM, write margin, cell current,
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A Self-Alignment Row-by-Row Variable-V_DD Scheme Reducing 90% of Active-Leakage Power in SRAM's Fayez Robert SALIBA Hiroshi KAWAGUCHI Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 743-748 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: active leakage, low power, SRAM,
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Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation Masaaki IIJIMA Masayuki KITAMURA Masahiro NUMA Akira TADA Takashi IPPOSHI Shigeto MAEGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 666-674 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: low power design, PD-SOI, body-bias, pass-transistor logic, circuit simulation, SRAM,
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Low-Voltage Embedded RAMs in Nanometer Era Takayuki KAWAHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 735-742 Type of Manuscript: INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Keyword: low-voltage, SRAM, DRAM, FD-SOI, twin-cell, embedded RAM,
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A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 ; pp. 3634-3641 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: SRAM, DVS, V_th-variation-tolerant, low power,
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A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing Junichi MIYAKOSHI Yuichiro MURACHI Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 ; pp. 1629-1636 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: SRAM, low power, parallel processing, image signal processing, H.264, MPEG,
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A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_th) Variation Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 ; pp. 1526-1534 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: SRAM, cell terminal biasing, differential cell terminal, SNM, write margin, disturb,
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New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications Chun-Lung HSU Mean-Hom HO Chin-Feng LIN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 ; pp. 377-384 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: current-mirror sense amplifier, high-speed, low-voltage, SRAM,
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0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier Toshikazu SUZUKI Yoshinobu YAMAGAMI Ichiro HATANAKA Akinori SHIBAYAMA Hironori AKAMATSU Hiroyuki YAMAUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 ; pp. 630-638 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Memory Keyword: SRAM, low-voltage, wide-voltage, SoC,
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Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage with High Random-Access Bandwidth and Large Storage Capacity Hans Jurgen MATTAUSCH Koji KISHI Takayuki GYOHTEN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/03/01 Vol. E84-C No. 3 ; pp. 410-417 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: multiple-ports, SRAM, cache, access bandwidth,
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A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/01/25 Vol. E83-C No. 1 ; pp. 109-114 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: cache, SRAM, low power, two-port, microprocessor,
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Current-Sensed SRAM Techniques for Megabit-Class Integration--Progress in Operating Frequency by Using Hidden Writing-Recovery Architecture-- Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/11/25 Vol. E82-C No. 11 ; pp. 2056-2064 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, high speed, writing-recovery, current sense, virtual-GND line, squashed memory cell,
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Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/25 Vol. E82-C No. 1 ; pp. 94-104 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, macrocell, size-configurable, high speed, low power, per-bitline architecture, current-sense amplifier, squashed memory cell, trench isolation,
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Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design Peter M. LEE Tsuyoshi SEO Kiyoshi ISE Atsushi HIRAISHI Osamu NAGASHIMA Shoji YOSHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/04/25 Vol. E81-C No. 4 ; pp. 595-601 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: hot-carrier degradation, reliability, device lifetime, circuit simulation, SRAM, DRAM,
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A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 ; pp. 1598-1607 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, low power, virtual GND, column address, synchronous, macrocell,
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A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs Hironori AKAMATSU Toru IWATA Hiroyuki YAMAUCHI Hisakazu KOTANI Akira MATSUZAWA Hiro YAMAMOTO Takashi HIRATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/25 Vol. E80-C No. 12 ; pp. 1572-1577 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: multiple-threshold, 1-volt, MT-CMOS, data storage circuit, SRAM, virtual power line, intermittent connection,
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A 6.93-µm² Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 ; pp. 590-596 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, full CMOS cell, local interconnect, TiN,
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Current Sense Amplifiers for Low-Voltage Memories Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/08/25 Vol. E79-C No. 8 ; pp. 1120-1130 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, ROM, current sensing, amplifier, low voltage,
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Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect Yasuo YAMAGUCHI Jun TAKAHASHI Takehisa YAMAGUCHI Tomohisa WADA Toshiaki IWAMATSU Hans-Oliver JOACHIM Yasuo INOUE Tadashi NISHIMURA Natsuro TSUBOUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 ; pp. 812-817 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: SOI, SIMOX, SRAM, low-voltage operation, back-gate bias effect,
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Monolithic Integration of Resonant Tunneling Diode and HEMT for Low-Voltage, Low-Power Digital Circuits Yuu WATANABE Yasuhiro NAKASHA Kenji IMANISHI Masahiko TAKIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/25 Vol. E78-C No. 4 ; pp. 368-373 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Device Technology Keyword: RTD, HEMT, SRAM, negative differential resistance, digital circuits,
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A Bipolar Divided Word-Line Scheme for a High-Speed and Large-Capacity BiCMOS SRAM Takakuni DOUSEKI Tadashi NAGAYAMA Yasuo OHMORI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/25 Vol. E75-C No. 11 ; pp. 1364-1368 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: BiCMOS, ECL interface, SRAM, ECL-CMOS,
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A Study of Delay Time on Bit Lines in Megabit SRAM's Atsushi KINOSHITA Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/25 Vol. E75-C No. 11 ; pp. 1383-1386 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: SRAM, coupling capacitance, bit-line,
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