IEICE Trans

Keyword : SIMD

Implementing 128-Bit Secure MPKC Signatures Ming-Shing CHEN Wen-Ding LI Bo-Yuan PENG Bo-Yin YANG Chen-Mou CHENG
Publication: Publication Date: 2018/03/01 Vol. E101-A No. 3 ; pp. 553-569 Type of Manuscript: PAPER Category: Cryptography and Information Security Keyword: MPKC signatures, finite field arithmetic, SIMD, additive FFT,
	Summary \| Full Text:PDF(2.1MB)

Efficient Parallel Join Processing Exploiting SIMD in Multi-Thread Environments Gilseok HONG Seonghyeon KANG Chang soo KIM Jun-Ki MIN
Publication: Publication Date: 2018/03/01 Vol. E101-D No. 3 ; pp. 659-667 Type of Manuscript: PAPER Category: Data Engineering, Web Information Systems Keyword: sort-merge join, SIMD, kernel density estimator, multi-thread,
	Summary \| Full Text:PDF(1.1MB)

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures Yaohua WANG Shuming CHEN Hu CHEN Jianghua WAN Kai ZHANG Sheng LIU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/02/01 Vol. E96-D No. 2 ; pp. 365-369 Type of Manuscript: LETTER Category: Computer System Keyword: SIMD, dual-core, scalar, vector,
	Summary \| Full Text:PDF(590.8KB)

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS Xun HE Xin JIN Minghui WANG Dajiang ZHOU Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2609-2618 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: SIMD, cache coherence, NoC, GMACs, multicore processor,
	Summary \| Full Text:PDF(3.6MB)

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems Takeshi KUMAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Masaharu TAGAMI Masakatsu ISHIZAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/09/01 Vol. E94-D No. 9 ; pp. 1742-1754 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: matrix-processing architecture, SIMD, bit-serial and word-parallel, CAM, table-lookup coding, cryptographic algorithm, AES,
	Summary \| Full Text:PDF(1.1MB)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 ; pp. 1409-1418 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: content addressable memory, CAM, matrix-processing architecture, SIMD, bit-serial and word-parallel, table-lookup coding, DCT, Huffman coding, JPEG,
	Summary \| Full Text:PDF(624KB)

A Partial Access Mechanism on a Register for Low-Cost Embedded Multimedia ASIP Ha-young JEONG Min-young CHO Won HUR Yong-surk LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/07/01 Vol. E91-C No. 7 ; pp. 1171-1174 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: embedded processor, ASIP, SIMD, partial access,
	Summary \| Full Text:PDF(270.6KB)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/08/01 Vol. E90-D No. 8 ; pp. 1312-1315 Type of Manuscript: LETTER Category: Image Processing and Video Processing Keyword: DCT, fast DCT, matrix-processing engine, SIMD, bit-serial and word-parallel,
	Summary \| Full Text:PDF(485KB)

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS Kazutami ARIMOTO Toshihiro HATTORI Hidehiro TAKATA Atsushi HASEGAWA Toru SHIMIZU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 657-665 Type of Manuscript: INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Keyword: low power, power management, DSP, SIMD,
	Summary \| Full Text:PDF(1.8MB)

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory Takeshi KUMAKI Yutaka KONO Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/01/01 Vol. E90-D No. 1 ; pp. 346-354 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: multiport, content addressable memory, CAM, parallel processing, SIMD, categorization, bit parallel block parallel, table-lookup-coding, Huffman coding,
	Summary \| Full Text:PDF(1.6MB)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 ; pp. 3623-3633 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: low power, motion estimation, H.264, SIMD, systolic array,
	Summary \| Full Text:PDF(1.9MB)

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture Toru SHIMIZU Masami NAKAJIMA Masahiro KAINAGA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 ; pp. 1512-1518 Type of Manuscript: INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: massively parallel processor, SIMD, fine-grained ALU, wideband bus,
	Summary \| Full Text:PDF(1.8MB)

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers Xizhen XU Sotirios G. ZIAVRAS
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/02/01 Vol. E89-D No. 2 ; pp. 639-646 Type of Manuscript: Special Section PAPER (Special Section on Parallel/Distributed Computing and Networking) Category: Parallel/Distributed Algorithms Keyword: configurable computing, FPGA, SIMD, parallel processing, memory switching, FFT, hardware-software codesign,
	Summary \| Full Text:PDF(417.3KB)

An MAMS-PP4: Multi-Access Memory System Used to Improve the Processing Speed of Visual Media Applications in a Parallel Processing System Hyung LEE Hyeon-Koo CHO Dae-Sang YOU Jong-Won PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/11/01 Vol. E87-A No. 11 ; pp. 2852-2858 Type of Manuscript: Special Section PAPER (Special Section on Concurrent Systems and Hybrid Systems) Category: Concurrent Systems Keyword: visual media processing, parallel processing system, multi-access memory system, SIMD,
	Summary \| Full Text:PDF(330.6KB)

An Acceleration Processor for Data Intensive Scientific Computing Cheong Ghil KIM Hong-Sik KIM Sungho KANG Shin Dug KIM Gunhee HAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/07/01 Vol. E87-D No. 7 ; pp. 1766-1773 Type of Manuscript: Special Section PAPER (Special Section on Hardware/Software Support for High Performance Scientific and Engineering Computing) Category: Scientific and Engineering Computing with Applications Keyword: SIMD, FPGA, artificial neural networks, diffusion equations, image processing,
	Summary \| Full Text:PDF(1.1MB)

High-Quality and Processor-Efficient Implementation of an MPEG-2 AAC Encoder Yuichiro TAKAMIZAWA Toshiyuki NOMURA Masao IKEKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/03/01 Vol. E86-D No. 3 ; pp. 418-424 Type of Manuscript: Special Section PAPER (Special Issue on Speech Information Processing) Category: Speech and Audio Coding Keyword: MPEG-2 AAC, audio, encoder, compression, SIMD,
	Summary \| Full Text:PDF(972.2KB)

A Programmable Geometry Processor with Enhanced Four-Parallel SIMD Type Processing Core for PC-Based 3D Graphics Hiroyuki KAWAI Yoshitsugu INOUE Junko KOBARA Robert STREITENBERGER Hiroaki SUZUKI Hiroyasu NEGISHI Masatoshi KAMEYAMA Kazunari INOUE Yasutaka HORIBA Kazuyasu FUJISHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/05/01 Vol. E85-C No. 5 ; pp. 1200-1210 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 3D graphics, programmable, geometry, SIMD, clip test,
	Summary \| Full Text:PDF(1.7MB)

Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products Naohiko IRIE Fumio ARAKAWA Kunio UCHIYAMA Shinichi YOSHIOKA Atsushi HASEGAWA Kevin IADONATE Mark DEBBAGE David SHEPHERD Margaret GEARTY
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 ; pp. 315-322 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: High-Performance Technologies Keyword: embedded processor, SIMD, preload, branch prediction,
	Summary \| Full Text:PDF(1.3MB)

SIMD ISA Extensions: Power Efficiency on Multimedia on a Superscalar Processor Julien SEBOT Nathalie DRACH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 ; pp. 297-303 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: multimedia, SIMD, superscalar, low power,
	Summary \| Full Text:PDF(465.8KB)

200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology Tatsuo TERUYAMA Tetsuo KAMADA Masashi SASAHARA Shardul KAZI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 ; pp. 235-242 Type of Manuscript: INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Keyword: microprocessor, MIPS, SIMD, tiling, network,
	Summary \| Full Text:PDF(864.2KB)

A Multimedia Architecture Extension for an Embedded RISC Processor Ichiro KURODA Kouhei NADEHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/09/01 Vol. E84-A No. 9 ; pp. 2255-2260 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: multimedia, RISC microprocessor, SIMD, inverse discrete cosine transform,
	Summary \| Full Text:PDF(803.5KB)

An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems Toshiaki INOUE Takashi MANABE Sunao TORII Satoshi MATSUSHITA Masato EDAHIRO Naoki NISHI Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/08/01 Vol. E84-C No. 8 ; pp. 1014-1020 Type of Manuscript: INVITED PAPER (Special Issue on Silicon Nanodevices) Category: Keyword: SIMD, multiplier, embedded microprocessor, on-chip multiprocessor, area-efficiency,
	Summary \| Full Text:PDF(2.5MB)

Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder Koyo NITTA Toshihiro MINAMI Toshio KONDO Takeshi OGURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/03/01 Vol. E84-D No. 3 ; pp. 317-325 Type of Manuscript: PAPER Category: VLSI Systems Keyword: motion estimation and compensation, scene-adaptive algorithm, MPEG-2 video encoder, hardware architecture, SIMD,
	Summary \| Full Text:PDF(4.3MB)

Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products Kunio UCHIYAMA Fumio ARAKAWA Yasuhiko SAITO Koki NOGUCHI Atsushi HASEGAWA Shinichi YOSHIOKA Naohiko IRIE Takeshi KITAHARA Mark DEBBAGE Andy STURGES
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 ; pp. 139-149 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: embedded processor, RISC, SIMD, system-on-chip, multimedia,
	Summary \| Full Text:PDF(1.6MB)

A 350 MHz 5.6 GOPS/1.4 GFLOPS 4-Way VLIW Embedded Microprocessor Hiroshi OKANO Atsuhiro SUGA Hideo MIYAKE Yoshimasa TAKEBE Yasuki NAKAMURA Hiromasa TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 ; pp. 150-156 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: VLIW, microprocessor, multimedia, SIMD, synthesis,
	Summary \| Full Text:PDF(823.7KB)

A Fixed-Point DSP (MDSP) Chip for Portable Multimedia Soohwan ONG Myung H. SUNWOO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-A No. 6 ; pp. 939-944 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: SIMD, vector processing, parallel architecture, video signal processing, digital signal processing,
	Summary \| Full Text:PDF(623.6KB)

5. 4 GOPS, 81 GB/s Linear Array Architecture DSP Akihiko HASHIGUCHI Masuyoshi KUROKAWA Ken'ichiro NAKAMURA Hiroshi OKUDA Koji AOYAMA Mitsuharu OHKI Katsunori SENO Ichiro KUMATA Masatoshi AIKAWA Hirokazu HANAKI Takao YAMAZAKI Mitsuo SONEDA Seiichiro IWASE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 ; pp. 661-668 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: video, parallel processing, SIMD, DSP,
	Summary \| Full Text:PDF(932.3KB)

An LSI for Low Bit-Rate Image Compression Using Vector Quantization Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 ; pp. 718-724 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: parallel processor, memory-based, vector quantization, low bit-rate image compression, low power, SIMD,
	Summary \| Full Text:PDF(748.2KB)

Optical Flow Detection System Using a Parallel Processor NEURO4 Jun TAKEDA Ken-ichi TANAKA Kazuo KYUMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 ; pp. 439-445 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: optical flow, moving image recognition, neural network, parallel processing, SIMD,
	Summary \| Full Text:PDF(604.9KB)

A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 ; pp. 970-975 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multi Processors Keyword: parallel processor, memory-base, vector quantization, low bit-rate image compression, SIMD,
	Summary \| Full Text:PDF(632KB)

A 3.2 GFLOPS Neural Network Accelerator Shinji KOMORI Yutaka ARIMA Yoshikazu KONDO Hirono TSUBOTA Ken-ichi TANAKA Kazuo KYUMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 ; pp. 859-867 Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Keyword: neural network, parallel processing, SIMD, LSI,
	Summary \| Full Text:PDF(909.1KB)

A Highly Parallel DSP Architecture for Image Recognition Hiroyuki KAWAI Yoshitsugu INOUE Rebert STREITENBERGER Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/08/25 Vol. E78-A No. 8 ; pp. 963-970 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: image recognition, SIMD, DSP, architecture,
	Summary \| Full Text:PDF(727.1KB)

7.5 MFLIPS Fuzzy Microprocessor Using SIMD and Logic-in-Memory Structure Mamoru SASAKI Fumio UENO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/25 Vol. E77-C No. 7 ; pp. 1075-1082 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: fuzzy if-then rule, fuzzy inference, SIMD, logic-in-memory, multi-operand operation,
	Summary \| Full Text:PDF(707.8KB)

Single-Board SIMD Processors Using Gate-Array LSIs for Parallel Processing Toshio KONDO Yoshimasa KIMURA Noboru SONEHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1827-1834 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: parallel processor, SIMD, gate-array, tree network,
	Summary \| Full Text:PDF(689KB)