Keyword : SDRAM

Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access
Lei GUO Yuhua TANG Yong DOU Yuanwu LEI Meng MA Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12 ; pp. 2765-2775
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
window memory layout scheme (WMLS), alternate row-wise/column-wise matrix access, SDRAM, GPU, FPGA, 
 Summary | Full Text:PDF
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
Kohei HOSOKAWA Katsunori TANAKA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2810-2817
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
FPGA-based hardware emulators, SDRAM, memory controller, clock generator, 
 Summary | Full Text:PDF
High-Level Synthesis with SDRAMs and RAMBUS DRAMs
Asheesh KHARE Preeti R. PANDA Nikil D. DUTT Alexandru NICOLAU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2347-2355
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
scheduling, CDFG, SDRAM, access modes, multiple banks, 
 Summary | Full Text:PDF
A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme
Hisashi IWAMOTO Naoya WATANABE Akira YAMAZAKI Seiji SAWADA Yasumitsu MURAI Yasuhiro KONISHI Hiroshi ITOH Masaki KUMANOYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1328-1333
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
synchronous DRAM, SDRAM, high speed DRAM, multiple-register, 
 Summary | Full Text:PDF