Keyword : RTL design

Conversion from Synchronous RTL Models to Asynchronous RTL Models
Shogo SEMBA Hiroshi SAITO 
Publication:   
Publication Date: 2019/07/01
Vol. E102-A  No. 7 ; pp. 904-913
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
asynchronous circuits, RTL design, conversion, XML, 
 Summary | Full Text:PDF(3MB)
RTL Design of High-Speed Sorted QR Decomposition for MIMO Decoder
Yuya MIYAOKA Yuhei NAGAO Masayuki KUROSAKI Hiroshi OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/11/01
Vol. E95-A  No. 11 ; pp. 1991-1997
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Communication Theory and Signals
Keyword: 
MIMO, QRD, sorted QRD, RTL design, 
 Summary | Full Text:PDF(1.5MB)
Low Complexity Compensation of Frequency Dependent I/Q Imbalance and Carrier Frequency Offset for Direct Conversion Receivers
Leonardo LANANTE, Jr. Masayuki KUROSAKI Hiroshi OCHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/02/01
Vol. E95-B  No. 2 ; pp. 484-492
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
carrier frequency offset, I/Q imbalance, RTL design, 
 Summary | Full Text:PDF(857.6KB)
A Proposition of 600 Mbps WLAN-Like System with Low-Complexity MIMO Decoder for FPGA Implementation
Wahyul Amien SYAFEI Yuhei NAGAO Ryuta IMASHIOYA Masayuki KUROSAKI Baiko SAI Hiroshi OCHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/02/01
Vol. E94-B  No. 2 ; pp. 491-498
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
FPGA, GLST, high throughput, MIMO, RTL design, WLAN, 
 Summary | Full Text:PDF(2.2MB)
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications
Konstantinos SIOZIOS George KOUTROUMPEZIS Konstantinos TATAS Nikolaos VASSILIADIS Vasilios KALENTERIDIS Haroula POURNARA Ilias PAPPAS Dimitrios SOUDRIS Antonios THANAILAKIS Spiridon NIKOLAIDIS Stilianos SISKOS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1369-1380
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
FPGA, circuit design, CAD tools, RTL design, configuration bitstream, 
 Summary | Full Text:PDF(1.3MB)
Power Modeling of Synthesizable Soft Macros
Kyung Tae DO Yang Hyo KIM Young Hwan KIM Jung Yun CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3091-3099
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
parameterized power model, synthesizable macro, RTL design, 
 Summary | Full Text:PDF(2.7MB)