Keyword : RISC


Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo SUGURE Seiji TAKEUCHI Yuichi ABE Hiromichi YAMADA Kazuya HIRAYANAGI Akihiko TOMITA Kesami HAGIWARA Takeshi KATAOKA Takanori SHIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 844-850
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
microcontrollerRISClow-latencyinterrupt response timesmaller code size
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A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
Tetsuya YAMADA Makoto ISHIKAWA Yuji OGATA Takanobu TSUNODA Takahiro IRITA Saneaki TAMAKI Kunihiko NISHIYAMA Tatsuya KAMEI Ken TATEZAWA Fumio ARAKAWA Takuichiro NAKAZAWA Toshihiro HATTORI Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 253-262
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processorlow powerRISCDSPMAC
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A 500-MHz Embedded Out-of-Order Superscalar Microprocessor
Masayuki DAITO Kazumasa SUZUKI Ken-ichi UEHIGASHI Hiroshi MORITA Hitoshi SONODA Nobuhito MORIKAWA Masatoshi MORIYAMA Shoichiro SATO Terumi FUKUDA Saori NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 243-252
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processorRISCout-of-ordersuperpipeline
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Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products
Kunio UCHIYAMA Fumio ARAKAWA Yasuhiko SAITO Koki NOGUCHI Atsushi HASEGAWA Shinichi YOSHIOKA Naohiko IRIE Takeshi KITAHARA Mark DEBBAGE Andy STURGES 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 139-149
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
embedded processorRISCSIMDsystem-on-chipmultimedia
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Single-Chip Implementation of a 32-bit Motor-Drive-Specific Microcontroller with Floating-Point Unit
Jin-Cheon KIM Sang-Hoon LEE Joo-Hyun LEE Do-Young LEE Won-Chang JUNG Hong-June PARK Im-Soo MOK Hyung-Gyun KIM Ga-Woo PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Processors
Keyword: 
motor drive32-bit microcontrollersingle-chipfloating-point unitRISCCMOS VLSI
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A Reconfigurable Digital Signal Processor
Boon Keat TAN Toru OGAWA Ryuji YOSHIMURA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1424-1430
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DSP processorreconfigurableflexibleprocessors arrayfault-tolerantASICdigital signal processingRISC
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Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1539-1545
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
RISCarchitecturelow powerhigh speedmicroprocessor
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Quad-Processor Redundancy for a RISC-Based Fault Tolerant Computer
Shinichiro YAMAGUCHI Tetsuaki NAKAMIKAWA Naoto MIYAZAKI Yuuichirou MORITA Yoshihiro MIYAZAKI Sakou ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 15-20
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Redundancy Techniques
Keyword: 
fault tolerancefault tolerant computerredundant systemdual systemhigh availabilityUNIXRISCtransaction processingopen system
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Hiding Data Cache Latency with Load Address Prediction
Toshinori SATO Hiroshige FUJII Seigo SUZUKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11 ; pp. 1523-1532
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
RISCcache memoryload-use hazardload latencyaddress prediction
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A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor
Hiroaki SUZUKI Toshichika SAKAI Hisao HARIGAI Yoichi YANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 389-393
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
RISCmicroprocessorCMOS LSIlow-power
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