Keyword : PLA


A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells
Ulkuhan EKINCIEL Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6 ; pp. 1159-1167
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
PLAmodule generatorcell generationHDL behavior generation
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A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits
Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 1069-1077
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLAhigh-speedarea-efficientdual-rail
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A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture
Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/02/01
Vol. E87-C  No. 2 ; pp. 238-245
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLAlogic celldual-railarray logicarea-efficient
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A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/09/01
Vol. E84-C  No. 9 ; pp. 1240-1246
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
high speedPLAarray logic circuitsense amplifier
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An Optimum Half-Hot Code Assignment Algorithm for Input Encoding and Its Application to Finite State Machines
Yasunori NAGATA Masao MUKAIDONO Chushin AFUSO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/10/25
Vol. E78-D  No. 10 ; pp. 1231-1238
Type of Manuscript:  PAPER
Category: Automata, Languages and Theory of Computing
Keyword: 
finite state machinehalf-hot codeinput encoding problemPLAunate Boolean function
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Fault Analysis on (K+1)-Valued PLA Structure Logic Circuits
Hui Min WANG Chung Len LEE Jwu E CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 1001-1010
Type of Manuscript:  PAPER
Category: Fault Analysis, Testing and Verification
Keyword: 
fault analysis (K+1)-valued logic circuitsPLAtwo-levelcircuit
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