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| Keyword : PFD
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A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6 ;
pp. 956-963
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, | | | Summary | Full Text:PDF | |
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A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm
Hyuk-Jun SUNG Kwang Sub YOON | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/02/25
Vol. E83-A
No. 2 ;
pp. 267-271
Type of Manuscript:
Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
dual-looped PLL, PFD, VCO, V-I converter, current-pumping algorithm, | | | Summary | Full Text:PDF | |
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