Keyword : PEAS-I system

An Instruction Set Optimization Algorithm for Pipelined ASIPs
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1707-1714
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIP, pipelined architecture, HW/SW partitioning, performance estimation, PEAS-I system, 
 Summary | Full Text:PDF
An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI Yoshimichi HONMA Jun SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 353-362
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
scheduling, pipeline hazards, HW/SW partitioning, ASIP, performance estimation, PEAS-I system, 
 Summary | Full Text:PDF