Keyword : OPC

Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device
Soo Han CHOI Young Hee PARK Chul Hong PARK Sang Hoon LEE Moon Hyun YOO Jun Dong CHO Gyu Tae KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5 ; pp. 658-661
Type of Manuscript:  BRIEF PAPER
Category: Memory Devices
Keyword: 
edge effects, analytic model, retargeting, shaping gate channels, OPC, leakage current, drive current, 
 Summary | Full Text:PDF(2.6MB)
Manufacturability-Aware Design of Standard Cells
Hirokazu MUTA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2682-2690
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
manufacturability, variability, DFM, ACLV, standard cell, OPC, RET, 
 Summary | Full Text:PDF(546.5KB)
The Front-End LSI with a 5-Tap PRML for 2 Reading and Writing of BD-R/RW/ROM
GoangSeog CHOI JumHan BAE HyunSoo PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 727-730
Type of Manuscript:  Special Section LETTER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
BD, LSI, PRML, OPC, Viterbi detector, 
 Summary | Full Text:PDF(653.1KB)
A Design Hierarchy of IC Interconnects and Gate Patterns
Shinji ODANAKA Akio MISAKA Kyoji YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 948-954
Type of Manuscript:  INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
TCAD, interconnect, OPC, gate pattern, design rule, 
 Summary | Full Text:PDF(950.2KB)