Keyword : NAND

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Seongjae CHO Jung Hoon LEE Yoon KIM Jang-Gn YUN Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5 ; pp. 596-601
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Flash/Advanced Memory
Keyword: 
NAND, flash memory, program inhibition, self-boosting, FinFET, device simulation, 
 Summary | Full Text:PDF
A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory
Myounggon KANG Ki-Tae PARK Youngsun SONG Sungsoo LEE Yunheub SONG Young-Ho LIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/02/01
Vol. E93-C  No. 2 ; pp. 182-186
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
NAND, FLASH, row decoder, high voltage switch, low voltage, area scaling, low power, 
 Summary | Full Text:PDF
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Yoon KIM Seongjae CHO Gil Sung LEE Il Han PARK Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5 ; pp. 653-658
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
NAND, flash memory, stacked NAND, vertical channel, 
 Summary | Full Text:PDF
Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAM, cascade, NAND, folded bitline, open bitline, die size, noise immunity, 
 Summary | Full Text:PDF
A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Hiromi NOBUKATA Kenichi SATORI Shinji HIRAMATSU Hideki ARAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 818-824
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory, NAND, folded bit line verify read, charge pump, 
 Summary | Full Text:PDF