Keyword : LUT cascade


BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
Munehiro MATSUURA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2762-2769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
incompletely specified functioncharacteristic functionbinary decision diagramfunctional decompositionLUT cascade
 Summary | Full Text:PDF(253.3KB)

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3471-3481
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
LUT cascadebdd_for_cffunctional decomposition
 Summary | Full Text:PDF(634KB)

A Design Algorithm for Sequential Circuits Using LUT Rings
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3342-3350
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
reconfigurable architectureLUT cascadeBDD_for_CFfunctional decomposition
 Summary | Full Text:PDF(699.9KB)

A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
LUT cascadeLUT ringmultiple-output functionreconfigurable logicprogrammable logic device
 Summary | Full Text:PDF(675.1KB)