Keyword : LDD


Design and Simulation of Asymmetric MOSFETs
Jong Pil KIM Woo Young CHOI Jae Young SONG Seongjae CHO Sang Wan KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5 ; pp. 978-982
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Junction Formation and TFT Reliability
Keyword: 
asymmetric MOSFETLDDmesa structuresidewall spacer gate
 Summary | Full Text:PDF

LATID (Large-Angle-Tilt Implanted Drain) FETs with Buried n- Profile for Deep-Submicron ULSIs
Junji HIRASE Takashi HORI Yoshinori ODAKE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3 ; pp. 350-354
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
MOSFETLDDn--gate overlapcircuit speedhot-carrier-induced degradation
 Summary | Full Text:PDF

A Highly Drivable CMOS Design with Very Narrow Sidewall and Novel Channel Profile for 3.3 V High Speed Logic Application
Jiro IDA Satoshi ISHII Youko KAJITA Tomonobu YOKOYAMA Masayoshi INO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4 ; pp. 525-531
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
CMOSLDDhot-carrier-reliabilitymultiplier
 Summary | Full Text:PDF