| Keyword : I/O-separated memory cell
|
A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme Nobutaro SHIBATA Takako ISHIHARA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C
No. 2 ;
pp. 316-330
Type of Manuscript:
PAPER
Category: Integrated Electronics Keyword: 4-way set-associative, cache-tag, CMOS, directed graph, dual-rail wordline, FD-SOI, I/O-separated memory cell, LRU, NRZ-type write-enable signal, SIMOX, SRAM, | | Summary | Full Text:PDF | |
|
|