Keyword : HDL-design environment


"FASTOOL" an FIR Filter Compiler Based on the Automatic Design of the Multi-Input-Adder
Takao YAMAZAKI Yoshihito KONDO Sayuri IGOTA Seiichiro IWASE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FIR filterfilter compilermulti-input-adderHDL-design environmentVerilog-HDL
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