| Keyword : FinFET
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Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method Sangheon OH Changhwan SHIN | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2016/05/01
Vol. E99-C
No. 5 ;
pp. 541-543
Type of Manuscript:
BRIEF PAPER
Category: Keyword: random variation, FinFET, SRAM, worst-case sampling, | | Summary | Full Text:PDF(720.2KB) | |
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Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices Katsuhiko TANAKA Kiyoshi TAKEUCHI Masami HANE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C
No. 4 ;
pp. 842-847
Type of Manuscript:
Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Device Keyword: FinFET, double gate, GIDL, device simulation, LSTP, | | Summary | Full Text:PDF(616.8KB) | |
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