Keyword : FPGA

Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches
Junnan LI Biao HAN Zhigang SUN Tao LI Xiaoyan WANG 
Publication:   
Publication Date: 2019/09/01
Vol. E102-B  No. 9 ; pp. 1862-1874
Type of Manuscript:  PAPER
Category: Transmission Systems and Transmission Equipment for Communications
Keyword: 
FPGA, packet parsing, packet-level parallelism, programable parser, 
 Summary | Full Text:PDF
An Architecture for Real-Time Retinex-Based Image Enhancement and Haze Removal and Its FPGA Implementation
Dabwitso KASAUKA Kenta SUGIYAMA Hiroshi TSUTSUI Hiroyuki OKUHATA Yoshikazu MIYANAGA 
Publication:   
Publication Date: 2019/06/01
Vol. E102-A  No. 6 ; pp. 775-782
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
real time processing, FPGA, Retinex-based image enhancement, haze removal, 
 Summary | Full Text:PDF
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers
Hiroki NAKAHARA Haruyoshi YONEKAWA Tomoya FUJII Masayuki SHIMODA Shimpei SATO 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5 ; pp. 1003-1011
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Tools
Keyword: 
machine learning, deep learning, pruning, FPGA, 
 Summary | Full Text:PDF
VHDL Design of a SpaceFibre Routing Switch
Alessandro LEONI Pietro NANNIPIERI Luca FANUCCI 
Publication:   
Publication Date: 2019/05/01
Vol. E102-A  No. 5 ; pp. 729-731
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
SpaceFibre, SpaceWire, RoutingSwitch, satellite networks, FPGA, 
 Summary | Full Text:PDF
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks
Cheng LUO Wei CAO Lingli WANG Philip H. W. LEONG 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5 ; pp. 1037-1045
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Applications
Keyword: 
deep learning, residual networks, software-hardware co-design, batch-normalization layers, FPGA, 
 Summary | Full Text:PDF
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA
Masayuki SHIMODA Shimpei SATO Hiroki NAKAHARA 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5 ; pp. 1020-1028
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Applications
Keyword: 
event-driven camera, object detector, all binarized convolutional neural network, FPGA, 
 Summary | Full Text:PDF
Automatic Generation Tool of FPGA Components for Robots
Takeshi OHKAWA Kazushi YAMASHINA Takuya MATSUMOTO Kanemitsu OOTSU Takashi YOKOTA 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5 ; pp. 1012-1019
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Tools
Keyword: 
FPGA, component oriented development, automatic generation, ROS, ROS-compliant FPGA component, robot, 
 Summary | Full Text:PDF
Fingertip-Size Optical Module, “Optical I/O Core”, and Its Application in FPGA
Takahiro NAKAMURA Kenichiro YASHIKI Kenji MIZUTANI Takaaki NEDACHI Junichi FUJIKATA Masatoshi TOKUSHIMA Jun USHIDA Masataka NOGUCHI Daisuke OKAMOTO Yasuyuki SUZUKI Takanori SHIMIZU Koichi TAKEMURA Akio UKITA Yasuhiro IBUSUKI Mitsuru KURIHARA Keizo KINOSHITA Tsuyoshi HORIKAWA Hiroshi YAMAGUCHI Junichi TSUCHIDA Yasuhiko HAGIHARA Kazuhiko KURATA 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4 ; pp. 333-339
Type of Manuscript:  INVITED PAPER (Special Section on Progress in Optical Device Technology for Increasing Data Transmission Capacity)
Category: 
Keyword: 
silicon photonics, bandwidth density, optical/electrical assembly, FPGA, 
 Summary | Full Text:PDF
Wideband Radar Frequency Measurement Receiver Based on FPGA without Mixer
Xinqun LIU Yingxiao ZHAO 
Publication:   
Publication Date: 2019/04/01
Vol. E102-D  No. 4 ; pp. 859-862
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
radar frequency measurement, DDC without mixer, FPGA, 
 Summary | Full Text:PDF
FPGA Implementation of a Real-Time Super-Resolution System Using Flips and an RNS-Based CNN
Taito MANABE Yuichiro SHIBATA Kiyoshi OGURI 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2280-2289
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, super-resolution, real-time, CNN, RNS, 
 Summary | Full Text:PDF
Lightweight Security Hardware Architecture Using DWT and AES Algorithms
Ignacio ALGREDO-BADILLO Francisco R. CASTILLO-SORIA Kelsey A. RAMÍREZ-GUTIÉRREZ Luis MORALES-ROSALES Alejandro MEDINA-SANTIAGO Claudia FEREGRINO-URIBE 
Publication:   
Publication Date: 2018/11/01
Vol. E101-D  No. 11 ; pp. 2754-2761
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
hardware, steganography, cryptography, DWT, FPGA, 
 Summary | Full Text:PDF
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers
Koya MITSUZUKA Michihiro KOIBUCHI Hideharu AMANO Hiroki MATSUTANI 
Publication:   
Publication Date: 2018/09/01
Vol. E101-D  No. 9 ; pp. 2258-2268
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, MapReduce, straggler, 
 Summary | Full Text:PDF
Analysis and Implementation of a QoS Optimization Method for Access Networks
Ling ZHENG Zhiliang QIU Weitao PAN Yibo MEI Shiyong SUN Zhiyi ZHANG 
Publication:   
Publication Date: 2018/09/01
Vol. E101-B  No. 9 ; pp. 1949-1960
Type of Manuscript:  PAPER
Category: Network System
Keyword: 
access network, quality of service, packet switching, buffer management, FPGA, 
 Summary | Full Text:PDF
Pixel Selection and Intensity Directed Symmetry for High Frame Rate and Ultra-Low Delay Matching System
Tingting HU Takeshi IKENAGA 
Publication:   
Publication Date: 2018/05/01
Vol. E101-D  No. 5 ; pp. 1260-1269
Type of Manuscript:  Special Section PAPER (Special Section on Machine Vision and its Applications)
Category: Machine Vision and its Applications
Keyword: 
high frame rate and ultra-low delay image processing, local binary feature based matching, keypoint orientation calculation, FPGA, 
 Summary | Full Text:PDF
A Hardware-Based Caching System on FPGA NIC for Blockchain
Yuma SAKAKIBARA Shin MORISHIMA Kohei NAKAMURA Hiroki MATSUTANI 
Publication:   
Publication Date: 2018/05/01
Vol. E101-D  No. 5 ; pp. 1350-1360
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
Blockchain, IoT, FPGA, cache, 
 Summary | Full Text:PDF
A Describing Method of an Image Processing Software in C for a High-Level Synthesis Considering a Function Chaining
Akira YAMAWAKI Seiichi SERIKAWA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 324-334
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology and Platform
Keyword: 
high-level synthesis, FPGA, describing method, image processing, function chaining, 
 Summary | Full Text:PDF
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device
Toshihiro KATASHITA Masakazu HIOKI Yohei HORI Hanpei KOIKE 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 303-313
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
Keyword: 
FPGA, programmable body biasing, evaluation platform, static power consumption, 
 Summary | Full Text:PDF
An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design
Akira JINGUJI Shimpei SATO Hiroki NAKAHARA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 354-362
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Emerging Applications
Keyword: 
machine learning, random forest, k-means clustering, FPGA, 
 Summary | Full Text:PDF
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing
Hoang-Gia VU Shinya TAKAMAEDA-YAMAZAKI Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 288-302
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
Keyword: 
checkpointing, FPGA, dependability, tree-based, 
 Summary | Full Text:PDF
A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA
Tomoya FUJII Shimpei SATO Hiroki NAKAHARA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 376-386
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Emerging Applications
Keyword: 
machine learning, deep learning, pruning, FPGA, 
 Summary | Full Text:PDF
FPGA Components for Integrating FPGAs into Robot Systems
Takeshi OHKAWA Kazushi YAMASHINA Hitomi KIMURA Kanemitsu OOTSU Takashi YOKOTA 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 363-375
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Emerging Applications
Keyword: 
FPGA, component-oriented development, ROS, ROS-compliant FPGA component, robot, 
 Summary | Full Text:PDF
Area Efficient Annealing Processor for Ising Model without Random Number Generator
Hidenori GYOTEN Masayuki HIROMOTO Takashi SATO 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 314-323
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
Keyword: 
combinatorial optimization problem, max-cut problem, Ising model, annealing, FPGA, 
 Summary | Full Text:PDF
Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor
Yu SUZUKI Masato ITO Satoshi KANDA Kousuke IMAMURA Yoshio MATSUDA Tetsuya MATSUMURA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12 ; pp. 2888-2900
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
optical flow, HOE algorithm, SOR, FPGA, processor, 
 Summary | Full Text:PDF
An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation
Kentaro KATO Somsak CHOOMCHUAY 
Publication:   
Publication Date: 2017/12/01
Vol. E100-D  No. 12 ; pp. 2953-2961
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, reed solomon decoder, error correcting code, time domain, 
 Summary | Full Text:PDF
Accelerating Weeder: A DNA Motif Search Tool Using the Micron Automata Processor and FPGA
Qiong WANG Mohamed EL-HADEDY Kevin SKADRON Ke WANG 
Publication:   
Publication Date: 2017/10/01
Vol. E100-D  No. 10 ; pp. 2470-2477
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
automata processor, Weeder, motif search, FPGA, 
 Summary | Full Text:PDF
An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA
Kenji KANAZAWA Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8 ; pp. 1807-1818
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, SAT, MaxSAT, WalkSAT, 
 Summary | Full Text:PDF
Comparative Evaluation of FPGA Implementation Alternatives for Real-Time Robust Ellipse Estimation based on RANSAC Algorithm
Theint Theint THU Jimpei HAMAMURA Rie SOEJIMA Yuichiro SHIBATA Kiyoshi OGURI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1409-1417
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
RANSAC, FPGA, Cramer's rule, Gauss-Jordan elimination, 
 Summary | Full Text:PDF
Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA
Makoto SAEN Tadanobu TOBA Yusuke KANNO 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 382-390
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
FPGA, soft-error tolerance, memory controller, configuration RAM, 
 Summary | Full Text:PDF
FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm
Henry BLOCK Tsutomu MARUYAMA 
Publication:   
Publication Date: 2017/02/01
Vol. E100-D  No. 2 ; pp. 256-264
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, hardware acceleration, phylogenetic tree reconstruction, maximum parsimony, 
 Summary | Full Text:PDF
An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach
Tatsuya KAWAMOTO Xin ZHOU Jacir L. BORDIM Yasuaki ITO Koji NAKANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 2901-2910
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
multiple-length-numbers, multiple-length-arithmetic, FPGA, RSA, montgomery modular multiplication, 
 Summary | Full Text:PDF
SLM: A Scalable Logic Module Architecture with Less Configuration Memory
Motoki AMAGASAKI Ryo ARAKI Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2500-2506
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, scalable logic module, technology mapping, 
 Summary | Full Text:PDF
Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology
Masakazu HIOKI Hanpei KOIKE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 3082-3089
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, programmable Vt, body biasing, static power, 
 Summary | Full Text:PDF
The Reliability Analysis of the 1-out-of-2 System in Which Two Modules Do Mutual Cooperation in Recovery Mode
Aromhack SAYSANASONGKHAM Satoshi FUKUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/09/01
Vol. E99-A  No. 9 ; pp. 1730-1734
Type of Manuscript:  LETTER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
1-out-of-2 system, reliability analysis, Markov chain, unreliability, parallel redundant system, hardware restoration, data reconstruction, mutual cooperation, FPGA, reconfiguration, 
 Summary | Full Text:PDF
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs
Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1294-1310
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan, 
 Summary | Full Text:PDF
Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1374-1380
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
logic synthesis, technology mapping, FPGA, SAT, 
 Summary | Full Text:PDF
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals
Yoshifumi KAWAMURA Naoya OKADA Yoshio MATSUDA Tetsuya MATSUMURA Hiroshi MAKINO Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/05/01
Vol. E99-A  No. 5 ; pp. 917-928
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, MCU peripherals, field programmable devices, sequencer, SRAM, 
 Summary | Full Text:PDF
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams
Yasin OGE Masato YOSHIMI Takefumi MIYOSHI Hideyuki KAWASHIMA Hidetsugu IRIE Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12 ; pp. 2207-2217
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, query processing, data stream, sliding-window aggregation, configurable hardware architecture, 
 Summary | Full Text:PDF
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
Shinya TAKAMAEDA-YAMAZAKI Hiroshi NAKATSUKA Yuichiro TANAKA Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12 ; pp. 2150-2158
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
soft processor, processor architecture, FPGA, 
 Summary | Full Text:PDF
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2658-2669
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
heterogeneous multicore, FPGA, custom accelerators, reconfigurable architecture, 
 Summary | Full Text:PDF
FPGA Hardware with Target-Reconfigurable Object Detector
Yoshifumi YAZAWA Tsutomu YOSHIMI Teruyasu TSUZUKI Tomomi DOHI Yuji YAMAUCHI Takayoshi YAMASHITA Hironobu FUJIYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/09/01
Vol. E98-D  No. 9 ; pp. 1637-1645
Type of Manuscript:  Special Section PAPER (Special Section on Optimization and Learning Algorithms of Small Embedded Devices and Related Software/Hardware Implementation)
Category: 
Keyword: 
dynamic reconfiguration of detection target, object detection, FPGA, 
 Summary | Full Text:PDF
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1392-1405
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX, 
 Summary | Full Text:PDF
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
Li-Chung HSU Masato MOTOMURA Yasuhiro TAKE Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4 ; pp. 288-297
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
TCI, ThruChip, 3-D FPGA, TSV, FPGA, TPR, VPR, 
 Summary | Full Text:PDF
Asynchronous Cellular Automaton Model of Spiral Ganglion Cell in the Mammalian Cochlea: Theoretical Analyses and FPGA Implementation
Masato IZAWA Hiroyuki TORIKAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/02/01
Vol. E98-A  No. 2 ; pp. 684-699
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
asynchronous cellular automaton, nonlinear response, spiral ganglion cell, mammalian cochlea, FPGA, 
 Summary | Full Text:PDF
Acceleration of the Fast Multipole Method on FPGA Devices
Hitoshi UKAWA Tetsu NARUMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 309-312
Type of Manuscript:  Special Section LETTER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
FPGA, fast multipole method, special-purpose pipeline, N-body simulation, 
 Summary | Full Text:PDF
Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration
Stewart DENHOLM Hiroaki INOUE Takashi TAKENAKA Tobias BECKER Wayne LUK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 288-297
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
data feed arbitration, acceleration, FPGA, low latency, finance, 
 Summary | Full Text:PDF
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC
Motoki AMAGASAKI Qian ZHAO Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 252-261
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
fault tolerant, FPGA, IP-core, 
 Summary | Full Text:PDF
A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 262-271
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
CAM, IP lookup, index generation unit, FPGA, 
 Summary | Full Text:PDF
Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration
Keisuke DOHI Koji OKINA Rie SOEJIMA Yuichiro SHIBATA Kiyoshi OGURI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 298-308
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
high-level synthesis, FPGA, stencil computation, heat conduction simulation, 
 Summary | Full Text:PDF
Real-Time Touch Controller with High-Speed Touch Accelerator for Large-Sized Touch Screens
SangHyuck BAE DoYoung JUNG CheolSe KIM KyoungMoon LIM Yong-Surk LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/01/01
Vol. E98-D  No. 1 ; pp. 193-196
Type of Manuscript:  LETTER
Category: Human-computer Interaction
Keyword: 
real-time, FPGA, parallel processing, digital filter, touch controller, capacitive touch, 
 Summary | Full Text:PDF
An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU
Ryota TAKASU Yoichi TOMIOKA Yutaro ISHIGAKI Ning LI Tsugimichi SHIBATA Mamoru NAKANISHI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/07/01
Vol. E97-C  No. 7 ; pp. 697-706
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Simulation Techniques and Their Applications for Electronics)
Category: 
Keyword: 
FDTD method, FPGA, parallel processing, SIMD array, 
 Summary | Full Text:PDF
FPGA Implementation of Exclusive Block Matching for Robust Moving Object Extraction and Tracking
Yoichi TOMIOKA Ryota TAKASU Takashi AOKI Eiichi HOSOYA Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3 ; pp. 573-582
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
object tracking, motion extraction, FPGA, synchronous shift data transfer, linear assignment, 
 Summary | Full Text:PDF
A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA
Duc-Hung LE Tran-Bao-Thuong CAO Katsumi INOUE Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/01/01
Vol. E97-C  No. 1 ; pp. 65-76
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
FPGA, Information Detection Hardware System, CAM, dual-port RAM, multi-match, image matching, 
 Summary | Full Text:PDF
A Digital TRNG Based on Cross Feedback Ring Oscillators
Lijuan LI Shuguo LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Vol. E97-A  No. 1 ; pp. 284-291
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Hardware Based Security
Keyword: 
digital TRNG, FPGA, stateless, metastability, chaos, 
 Summary | Full Text:PDF
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2576-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multicore processor, FPGA, Multimedia processing, High-performance-computing, 
 Summary | Full Text:PDF
Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access
Lei GUO Yuhua TANG Yong DOU Yuanwu LEI Meng MA Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12 ; pp. 2765-2775
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
window memory layout scheme (WMLS), alternate row-wise/column-wise matrix access, SDRAM, GPU, FPGA, 
 Summary | Full Text:PDF
Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process
Duc-Hung LE Katsumi INOUE Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/09/01
Vol. E96-A  No. 9 ; pp. 1883-1888
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, ASIC, matching system, Content Addressable Memory (CAM), multi-match, exact pattern matching, 
 Summary | Full Text:PDF
FPGA Design Framework Combined with Commercial VLSI CAD
Qian ZHAO Kazuki INOUE Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1602-1612
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGA, CAD, routing, 
 Summary | Full Text:PDF
A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards
Son-Truong NGUYEN Masaaki KONDO Tomoya HIRAO Koji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1645-1653
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
many-core processor, evaluation platform, prototyping, FPGA, 
 Summary | Full Text:PDF
FPGA Implementation of Human Detection by HOG Features with AdaBoost
Keisuke DOHI Kazuhiro NEGI Yuichiro SHIBATA Kiyoshi OGURI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1676-1684
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
histogram of oriented gradients, AdaBoost, human detection, FPGA, 
 Summary | Full Text:PDF
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1632-1644
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
FPGA, reconfigurable LSI, self-timed circuit, asynchronous circuit, 
 Summary | Full Text:PDF
Low Complexity Keypoint Extraction Based on SIFT Descriptor and Its Hardware Implementation for Full-HD 60 fps Video
Takahiro SUZUKI Takeshi IKENAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6 ; pp. 1376-1383
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
keypoint extraction, SIFT, hardware implementation, FPGA, parallelizing, 
 Summary | Full Text:PDF
Adaptive Analog-to-Information Converter Design with Limited Random Sequence Modulation
Chao ZHANG Jialuo XIAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2 ; pp. 469-476
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
adaptive AIC, analog-to-information converter, limited random sequence, prototype system, FPGA, 
 Summary | Full Text:PDF
Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2199-2207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
FPGA, low power, switch box, routing, 
 Summary | Full Text:PDF
Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration
Yoshihiro ICHINOMIYA Tsuyoshi KIMURA Motoki AMAGASAKI Morihiro KUGA Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2347-2356
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
FPGA, partial reconfiguration, fault-injection analysis, soft-error, dependability, 
 Summary | Full Text:PDF
FPGA Design of User Monitoring System for Display Power Control
Tomoaki ANDO Vasily G. MOSHNYAGA Koji HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2364-2372
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
seven-segment rectangular template, between the eyes region, eye-detection, user monitoring, FPGA, display, power management, 
 Summary | Full Text:PDF
Design and Implementation of a Handshake Join Architecture on FPGA
Yasin OGE Takefumi MIYOSHI Hideyuki KAWASHIMA Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12 ; pp. 2919-2927
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
FPGA, data stream processing, window join operator, accelerator, handshake join, 
 Summary | Full Text:PDF
An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors
Se-yong RO Lin-bo LUO Jong-wha CHONG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/11/01
Vol. E95-D  No. 11 ; pp. 2682-2692
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
Image warping, look-up table, perspective transformation, panorama unrolling, FPGA, 
 Summary | Full Text:PDF
Finite Virtual State Machines
Raouf SENHADJI-NAVARRO Ignacio GARCIA-VARGAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10 ; pp. 2544-2547
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
finite state machine, reconfiguration, RAM, FPGA, 
 Summary | Full Text:PDF
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory
Duc-Hung LE Katsumi INOUE Masahiro SOWA Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/10/01
Vol. E95-A  No. 10 ; pp. 1708-1717
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, information detection, content addressable memory, random access memory, parallel operation, multi-match, 
 Summary | Full Text:PDF
Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects
Mohammad Taghi TEIMOORI Ali JAHANIAN Adel DOKHANCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/10/01
Vol. E95-C  No. 10 ; pp. 1610-1619
Type of Manuscript:  Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies)
Category: 
Keyword: 
microwave on-chip interconnect, FPGA, performance, 
 Summary | Full Text:PDF
Neuron-Like Responses and Bifurcations of a Generalized Asynchronous Sequential Logic Spiking Neuron Model
Takashi MATSUBARA Hiroyuki TORIKAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8 ; pp. 1317-1328
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
neuron model, nonlinear dynamics, bifurcation phenomena, asynchronous sequential logic circuit, asynchronous cellular automaton, FPGA, 
 Summary | Full Text:PDF
A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions
Yusaku KANETA Shingo YOSHIZAWA Shin-ichi MINATO Hiroki ARIMURA Yoshikazu MIYANAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/07/01
Vol. E95-D  No. 7 ; pp. 1847-1857
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, string matching, regular expression matching, bit-parallel algorithm, event stream processing, 
 Summary | Full Text:PDF
Development of a Microwave Exciter for 87Sr+ Ion Frequency Standards
Iku HIRANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/07/01
Vol. E95-C  No. 7 ; pp. 1231-1233
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
highly stable microwave exciter, frequency stability, analog lead-lag filter, FPGA, 
 Summary | Full Text:PDF
Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion
Van-Phuc HOANG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/06/01
Vol. E95-A  No. 6 ; pp. 999-1006
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
LUT-based computation, truncated multiplier, FPGA, color space conversion, 
 Summary | Full Text:PDF
Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
Rongchun LI Yong DOU Yuanwu LEI Shice NI Song GUO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/05/01
Vol. E95-B  No. 5 ; pp. 1602-1611
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
multi-standard, radix-4, Viterbi decoder, FPGA, 
 Summary | Full Text:PDF
Asynchronous Circuit Design on Field Programmable Gate Array Devices
Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 516-522
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous, bundled-data, burst-mode, extended burst-mode, FPGA, generalized C-element, HDL, self-timed, 
 Summary | Full Text:PDF
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 546-554
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
power gating, gate-level, pipeline, self synchronous, energy minimum operation, FPGA, 
 Summary | Full Text:PDF
FPGA Implementation of Metastability-Based True Random Number Generator
Hisashi HATA Shuichi ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 426-436
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
TRNG, synchronous digital circuit, FPGA, entropy, 
 Summary | Full Text:PDF
Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF
Jeich MAR Chi-Cheng KUO Shin-Ru WU You-Rong LIN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 413-425
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
FPGA, MFMO, SDR, CR, ESPRIT, CORDIC, 
 Summary | Full Text:PDF
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 364-373
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
regular expression, NFA, DFA, MNFAU, FPGA, 
 Summary | Full Text:PDF
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks
Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 324-334
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA, 
 Summary | Full Text:PDF
Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 314-323
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGA, low power, region, hierarchical design, power consumption, 
 Summary | Full Text:PDF
Efficient Sequential Architecture of AES CCM for the IEEE 802.16e
Jae Deok JI Seok Won JUNG Jongin LIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/01/01
Vol. E95-D  No. 1 ; pp. 185-187
Type of Manuscript:  Special Section LETTER (Special Section on Trust, Security and Privacy in Computing and Communication Systems)
Category: Privacy
Keyword: 
cryptography, communication system security, integrated chip design, FPGA, 
 Summary | Full Text:PDF
Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 22 MIMO-OFDM System in 5.2-GHz Band
Hisayoshi KANO Shingo YOSHIZAWA Takashi GUNJI Shougo OKAMOTO Morio TAWARAYAMA Yoshikazu MIYANAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12 ; pp. 2400-2408
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
IEEE802.11ac, wideband MIMO-OFDM, FPGA, field experiment, 
 Summary | Full Text:PDF
Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2628-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation, 
 Summary | Full Text:PDF
Multi-Operand Adder Synthesis Targeting FPGAs
Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2579-2586
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
multi-operand adder, generalized parallel counter, arithmetic synthesis, FPGA, 
 Summary | Full Text:PDF
Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2519-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
FPGA, low power, power domain, power consumption, 
 Summary | Full Text:PDF
A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones
Md. Nazrul Islam MONDAL Koji NAKANO Yasuaki ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12 ; pp. 2378-2388
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
FPGA, block RAMs, asynchronous read operations, rewriting algorithm, 
 Summary | Full Text:PDF
FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic
Yuanwu LEI Yong DOU Jie ZHOU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/11/01
Vol. E94-D  No. 11 ; pp. 2173-2183
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
variable-precision floating-point (VP) arithmetic, Very Long Instruction Word (VLIW), elementary function, Newton's method, polynomial approximation, FPGA, 
 Summary | Full Text:PDF
3D-DCT Processor and Its FPGA Implementation
Yuki IKEGAKI Toshiaki MIYAZAKI Stanislav G. SEDUKHIN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7 ; pp. 1409-1418
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
3D-DCT, array processors, data manipulation, FPGA, 
 Summary | Full Text:PDF
ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave
Hiroomi HIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/07/01
Vol. E94-A  No. 7 ; pp. 1581-1584
Type of Manuscript:  LETTER
Category: Cryptography and Information Security
Keyword: 
direct digital frequency synthesizer, phase to amplitude converter, sine approximation, FPGA, 
 Summary | Full Text:PDF
A Proposition of 600 Mbps WLAN-Like System with Low-Complexity MIMO Decoder for FPGA Implementation
Wahyul Amien SYAFEI Yuhei NAGAO Ryuta IMASHIOYA Masayuki KUROSAKI Baiko SAI Hiroshi OCHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/02/01
Vol. E94-B  No. 2 ; pp. 491-498
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
FPGA, GLST, high throughput, MIMO, RTL design, WLAN, 
 Summary | Full Text:PDF
How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation
Daisuke SUZUKI Tsutomu MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 211-222
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Implementation
Keyword: 
hardware architecture, modular exponentiation, Montgomery multiplication, FPGA, DSP, 
 Summary | Full Text:PDF
A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation
Yoshiki YUNBE Masayuki MIYAMA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12 ; pp. 3284-3293
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
affine motion model, motion estimation, video segmentation, real-time processing, VLSI, FPGA, 
 Summary | Full Text:PDF
Accelerating Boolean Matching Using Bloom Filter
Chun ZHANG Yu HU Lingli WANG Lei HE Jiarong TONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/10/01
Vol. E93-A  No. 10 ; pp. 1775-1781
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, Boolean matching, Bloom filter, SAT, re-synthesis, 
 Summary | Full Text:PDF
A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard
Min Li HUANG Jin LEE Hendra SETIAWAN Hiroshi OCHI Sin-Chong PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/04/01
Vol. E93-B  No. 4 ; pp. 948-960
Type of Manuscript:  PAPER
Category: Terrestrial Radio Communications
Keyword: 
IEEE 802.11e, MAC, EDCA, FPGA, 
 Summary | Full Text:PDF
A Fast and Memory Efficient SPIHT Image Encoder
Zhong-Ho CHEN Alvin W. Y. SU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/03/01
Vol. E93-D  No. 3 ; pp. 602-610
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
image coding, wavelet, set-partition in hierarchical trees (SPIHT), FPGA, 
 Summary | Full Text:PDF | Errata[Uploaded on May 1,2010]
Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture
Cao LIANG Xinming HUANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 407-415
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architecture, parallel FFT, energy efficiency, ASIC, FPGA, DSP, 
 Summary | Full Text:PDF
High-Speed Passphrase Search System for PGP
Koichi SHIMIZU Daisuke SUZUKI Toyohiro TSURUMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A  No. 1 ; pp. 202-209
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Application
Keyword: 
passphrase, search, FPGA, PGP, security, 
 Summary | Full Text:PDF
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3268-3275
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
FPGA, technology mapping, cut enumeration, 
 Summary | Full Text:PDF
Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate
Anh-Tuan HOANG Katsuhiro YAMAZAKI Shigeru OYANAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/10/01
Vol. E92-D  No. 10 ; pp. 2034-2042
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
cryptography, SHA-2, fine-grained pipelining, FPGA, 
 Summary | Full Text:PDF
Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning
Teng LIN Jianhua FENG Dunshan YU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 1197-1199
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
FPGA, application-dependent testing, line branch, Test Configuration, 
 Summary | Full Text:PDF
PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPS
Tran Ngoc THINH Surin KITTITORNKUN Shigenori TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 1049-1061
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
Cuckoo Hashing, dynamic update, pattern matching, FPGA, NIDS/NIPS, 
 Summary | Full Text:PDF
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/04/01
Vol. E92-D  No. 4 ; pp. 575-583
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
network-on-chip, FPGA, customize, router, 
 Summary | Full Text:PDF
FPGA Implementation of Highly Modular Fast Universal Discrete Transforms
Panan POTIPANTONG Phaophak SIRISUK Soontorn ORAINTARA Apisak WORAPISHET 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 576-586
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
UDFHT, DHT, DST, DFT, DCT, FFT, FPGA, reconfigurable computing, 
 Summary | Full Text:PDF
Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device
Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3612-3621
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
fault tolerance, dependable, FPGA, reconfigurable device, soft error, 
 Summary | Full Text:PDF
Adaptive Impedance Matching System Using FPGA Processor for Efficient Control Algorithm
Hirokazu OBA Minseok KIM Ryotaro TAMAKI Hiroyuki ARAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/08/01
Vol. E91-C  No. 8 ; pp. 1348-1355
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
antenna input impedance, automatic matching system, FPGA, 
 Summary | Full Text:PDF
Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation
Yoshiaki YOKOYAMA Minseok KIM Hiroyuki ARAI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/04/01
Vol. E91-B  No. 4 ; pp. 1068-1075
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
systolic array, QR decomposition, RLS, CORDIC, FPGA, 
 Summary | Full Text:PDF
Hardware Neural Network for a Visual Inspection System
Seungwoo CHUN Yoshihiro HAYAKAWA Koji NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 935-942
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
hardware, visual inspection system, back-propagation, PCI-BUS, FPGA, 
 Summary | Full Text:PDF
A Design of the Signal Processing Hardware Platform for Communication Systems
Byung Wook LEE Sung Ho CHO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/03/01
Vol. E91-B  No. 3 ; pp. 939-942
Type of Manuscript:  LETTER
Category: Wireless Communication Technologies
Keyword: 
OFDM, IEEE 802.16, FPGA, DSP, platform, 
 Summary | Full Text:PDF
Implementation of Joint Pre-FFT Adaptive Array Antenna and Post-FFT Space Diversity Combining for Mobile ISDB-T Receiver
Dang Hai PHAM Jing GAO Takanobu TABATA Hirokazu ASATO Satoshi HORI Tomohisha WADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/01/01
Vol. E91-B  No. 1 ; pp. 127-138
Type of Manuscript:  Special Section PAPER (Special Section on Cognitive Radio and Spectrum Sharing Technology)
Category: Enabling Technology
Keyword: 
adaptive array antenna, space diversity combining, OFDM, ISDB-T, FPGA, DSP, 
 Summary | Full Text:PDF
Diversification of Processors Based on Redundancy in Instruction Set
Shuichi ICHIKAWA Takashi SAWADA Hisashi HATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 211-220
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Implementation
Keyword: 
FPGA, embedded systems, instruction set, randomization, secure processor, 
 Summary | Full Text:PDF
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1914-1922
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
Networks-on-Chip, FPGA, router, port combination, 
 Summary | Full Text:PDF
A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform
Chang-Seok CHOI Hanho LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1932-1938
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
partial reconfiguration, self-reconfiguration, adaptive FIR filter, FPGA, 
 Summary | Full Text:PDF
FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet
Toshihiro KATASHITA Yoshinori YAMAGUCHI Atusi MAEDA Kenji TODA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1923-1931
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
intrusion detection system, intrusion protection system, exact string matching, FPGA, 10 Gigabit Ethernet, 
 Summary | Full Text:PDF
Multiple Sequence Alignment Based on Dynamic Programming Using FPGA
Shingo MASUNO Tsutomu MARUYAMA Yoshiki YAMAGUCHI Akihiko KONAGAYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1939-1946
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
multiple sequence alignment, dynamic programming, FPGA, reconfiguration, 
 Summary | Full Text:PDF
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA
Takashi KAWANAMI Masakazu HIOKI Yohei MATSUMOTO Toshiyuki TSUTSUMI Tadashi NAKAGAWA Toshihiro SEKIGAWA Hanpei KOIKE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1947-1955
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
FPGA, low-power, threshold voltage control, body bias, 
 Summary | Full Text:PDF
A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1919-1926
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Low-Power and High-Performance VLSI Circuit Technology
Keyword: 
variation-aware, reconfigurable device, FPGA, yield, DFM, 
 Summary | Full Text:PDF
Basic Characteristics and Learning Potential of a Digital Spiking Neuron
Hiroyuki TORIKAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/10/01
Vol. E90-A  No. 10 ; pp. 2093-2100
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Neuron and Neural Networks
Keyword: 
spiking neuron, digital dynamical system, learning, UWB, FPGA, 
 Summary | Full Text:PDF
Wide View Imaging System Using Eight Random Access Image Sensors
Kenji IDE Ryusuke KAWAHARA Satoshi SHIMIZU Takayuki HAMAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1884-1891
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Image Sensor/Vision Chip
Keyword: 
smart image sensor, wide view imaging, object tracking, FPGA, background subtraction, 
 Summary | Full Text:PDF
Efficient Motion Estimation for H.264 Codec by Using Effective Scan Ordering
Jeongae PARK Misun YOON Hyunchul SHIN 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/07/01
Vol. E90-B  No. 7 ; pp. 1839-1843
Type of Manuscript:  LETTER
Category: Devices/Circuits for Communications
Keyword: 
motion estimation, absolute difference, H.264, FPGA, 
 Summary | Full Text:PDF
Design Methods of Radix Converters Using Arithmetic Decompositions
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/06/01
Vol. E90-D  No. 6 ; pp. 905-914
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
radix converter, LUT cascades, FPGA, functional decomposition, 
 Summary | Full Text:PDF
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os
Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5 ; pp. 924-931
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
circuit partitioning, time-multiplexed I/O, FPGA, pin constraint, 
 Summary | Full Text:PDF
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations
Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 699-707
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
within-die variation, reconfigurable device, FPGA, LUT (look-up table), yield, 
 Summary | Full Text:PDF
A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition
Yong KIM Hong JEONG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/02/01
Vol. E90-D  No. 2 ; pp. 562-568
Type of Manuscript:  PAPER
Category: Speech and Hearing
Keyword: 
speech recognition, hidden Markov model (HMM), two-level dynamic programming (TLDP), FPGA, 
 Summary | Full Text:PDF
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3510-3518
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
LUT cascades, 2nd-order Chebyshev approximation, non-uniform segmentation, NFGs, automatic synthesis, FPGA, 
 Summary | Full Text:PDF
Fast FPGA-Emulation-Based Simulation Environment for Custom Processors
Yuichi NAKAMURA Kouhei HOSOKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3464-3470
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
custom processor, simulation, emulation, FPGA, 
 Summary | Full Text:PDF
Joint Hardware-Software Implementation of Adaptive Array Antenna for ISDB-T Reception
Dang Hai PHAM Takanobu TABATA Hirokazu ASATO Satoshi HORI Tomohisa WADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/12/01
Vol. E89-B  No. 12 ; pp. 3215-3224
Type of Manuscript:  Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
array antenna, OFDM, ISDB-T, MRC, SMI, FPGA, DSP, 
 Summary | Full Text:PDF
Implementation of Multi-Channel Modem for DSRC System on Signal Processing Platform for Software Defined Radio
Akihisa YOKOYAMA Hiroshi HARADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/12/01
Vol. E89-B  No. 12 ; pp. 3225-3232
Type of Manuscript:  Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
software defined radio, signal processing, FPGA, ITS, DSRC, 
 Summary | Full Text:PDF
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm
Ryoichiro ATONO Shuichi ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/07/01
Vol. E89-D  No. 7 ; pp. 2301-2305
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
FPGA, custom circuit, partial evaluation, specialization, cryptography, embedded system, 
 Summary | Full Text:PDF
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule
Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 969-978
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-density parity-check codes, partially-parallel LDPC decoder, message-passing algorithm, FPGA, 
 Summary | Full Text:PDF
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA
Hui QIN Tsutomu SASAO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3 ; pp. 1139-1147
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
AES encryption, pipelined partial rolling (PPR), FPGA, 
 Summary | Full Text:PDF
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping
Canh Quang TRAN Hiroshi KAWAGUCHI Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 280-286
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Low Power Techniques
Keyword: 
FPGA, low power, low leakage, VDD hopping, Zigzag power-gating, 
 Summary | Full Text:PDF
A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers
Xizhen XU Sotirios G. ZIAVRAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/02/01
Vol. E89-D  No. 2 ; pp. 639-646
Type of Manuscript:  Special Section PAPER (Special Section on Parallel/Distributed Computing and Networking)
Category: Parallel/Distributed Algorithms
Keyword: 
configurable computing, FPGA, SIMD, parallel processing, memory switching, FFT, hardware-software codesign, 
 Summary | Full Text:PDF
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture
Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3516-3522
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
stereo vision, FPGA, scheduling, allocation, 
 Summary | Full Text:PDF
Frequency-Scaling Approach for Managing Power Consumption in NOCs
Chun-Lung HSU Wen-Tso WANG Ying-Fu HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3580-3583
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
frequency-scaling, low power, NOC, FPGA, 
 Summary | Full Text:PDF
Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937
Shiro KONUMA Shuichi ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2876-2879
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
custom circuit, simulation, random number, Mersenne Twister, FPGA, 
 Summary | Full Text:PDF
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages
Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3298-3305
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
reconfigurable processor, FPGA, multiple-supply-voltage scheme, 
 Summary | Full Text:PDF
A Reconfigurable Packet Routing-Oriented Signal Processing Platform
Akihisa YOKOYAMA Hitoshi INOUE Hiroshi HARADA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/11/01
Vol. E88-B  No. 11 ; pp. 4194-4203
Type of Manuscript:  Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
software defined radio, signal processing, FPGA, DSRC, 
 Summary | Full Text:PDF
A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications
Konstantinos SIOZIOS George KOUTROUMPEZIS Konstantinos TATAS Nikolaos VASSILIADIS Vasilios KALENTERIDIS Haroula POURNARA Ilias PAPPAS Dimitrios SOUDRIS Antonios THANAILAKIS Spiridon NIKOLAIDIS Stilianos SISKOS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1369-1380
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
FPGA, circuit design, CAD tools, RTL design, configuration bitstream, 
 Summary | Full Text:PDF
Header Extraction and Control for an Asynchronous Optical Packet Switch Based on DPSK Decoding
Dimitrios KLONIDIS Christina T. POLITI Reza NEJABATI Mike J. O'MAHONY Dimitra SIMEONIDOU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/05/01
Vol. E88-B  No. 5 ; pp. 1876-1883
Type of Manuscript:  Special Section PAPER (Joint Special Section on Recent Progress in Optoelectronics and Communications)
Category: Optical Network Architecture
Keyword: 
optical packet switching, optical DPSK, switch control, FPGA, 
 Summary | Full Text:PDF
FPGAs with Multidimensional Switch Topology
Yohei MATSUMOTO Akira MASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/04/01
Vol. E88-D  No. 4 ; pp. 775-778
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
FPGA, multidimensional topology, number of switches, Rent's rule, 
 Summary | Full Text:PDF
FPGA-Based Reconfigurable Adaptive FEC
Kazunori SHIMIZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3036-3046
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
dynamic reconfigurable system, adaptive FEC, FPGA, Reed Solomon codes, 
 Summary | Full Text:PDF
Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture
Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1897-1902
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable architecture, FPGA, bit-serial architecture, 
 Summary | Full Text:PDF
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity
Takashi KAWANAMI Masakazu HIOKI Hiroshi NAGASE Toshiyuki TSUTSUMI Tadashi NAKAGAWA Toshihiro SEKIGAWA Hanpei KOIKE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8 ; pp. 2004-2010
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
FPGA, reconfigurable device, low-power, threshold voltage control, EDA, 
 Summary | Full Text:PDF
Self-Reconfigurable Multi-Layer Neural Networks with Genetic Algorithms
Eiko SUGAWARA Masaru FUKUSHI Susumu HORIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8 ; pp. 2021-2028
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
self-reconfiguration, multi-layer neural network, weight training by genetic algorithm, FPGA, 
 Summary | Full Text:PDF
A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation
Young-Ho SEO Wang-Hyun KIM Ji-Sang YOO Dai-Gyoung KIM Dong-Wook KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8 ; pp. 2110-2119
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
DWT, wavelet, compression, FPGA, design, hardware, 
 Summary | Full Text:PDF
An FPGA-Based Acceleration Method for Metabolic Simulation
Yasunori OSANA Tomonori FUKUSHIMA Masato YOSHIMI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8 ; pp. 2029-2037
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
metabolic simulation, ordinary differential equations, FPGA, 
 Summary | Full Text:PDF
The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem
Shoji YAMAMOTO Shuichi ICHIKAWA Hiroshi YAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8 ; pp. 2038-2047
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
FPGA, custom circuit, graph algorithm, NP-complete, partial evaluation, 
 Summary | Full Text:PDF
An Acceleration Processor for Data Intensive Scientific Computing
Cheong Ghil KIM Hong-Sik KIM Sungho KANG Shin Dug KIM Gunhee HAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/07/01
Vol. E87-D  No. 7 ; pp. 1766-1773
Type of Manuscript:  Special Section PAPER (Special Section on Hardware/Software Support for High Performance Scientific and Engineering Computing)
Category: Scientific and Engineering Computing with Applications
Keyword: 
SIMD, FPGA, artificial neural networks, diffusion equations, image processing, 
 Summary | Full Text:PDF
FPGA Design of Real-Time Watermarking Processor for 2DDWT-Based Video Compression
Young-Ho SEO Dong-Wook KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6 ; pp. 1297-1304
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category: 
Keyword: 
image watermarking, DWT, FPGA, hardware implementation, co-operation with compressor, 
 Summary | Full Text:PDF
An Equalization Technique for 54 Mbps OFDM Systems
Naihua YUAN Anh DINH Ha H. NGUYEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 610-618
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
time domain equalization, OFDM, LDLT and LU decompositions, IEEE 802.11a, FPGA, pipeline FFT, 
 Summary | Full Text:PDF
Feasibility Study on Over-the-Air Software Download for Software-Radio-Based Intelligent Transport Systems
Hiroshi HARADA Masayuki FUJISE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/12/01
Vol. E86-B  No. 12 ; pp. 3425-3432
Type of Manuscript:  Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
software radio, ITS, over-the-air download, FPGA, multimode terminal, 
 Summary | Full Text:PDF
Trade-Offs in Custom Circuit Designs for Subgraph Isomorphism Problems
Shuichi ICHIKAWA Hidemitsu SAITO Lerdtanaseangtham UDORN Kouji KONISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/07/01
Vol. E86-D  No. 7 ; pp. 1250-1257
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
NP-complete, graph, algorithm, FPGA, 
 Summary | Full Text:PDF
Time-Memory Trade-off Cryptanalysis for Limited Key on FPGA-Based Parallel Machine RASH
Katsumi TAKAHASHI Hiroai ASAMI Katsuto NAKAJIMA Masahiro IIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5 ; pp. 781-788
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
RASH, FPGA, reconfigurable computing, time-memory trade-off cryptanalysis, 
 Summary | Full Text:PDF
Data Dependent Circuit for Subgraph Isomorphism Problem
Shuichi ICHIKAWA Shoji YAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5 ; pp. 796-802
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
NP-complete, custom circuit, FPGA, graph algorithm, 
 Summary | Full Text:PDF
Random Number Generators Implemented with Neighborhood-of-Four, Non-locally Connected Cellular Automata
Barry SHACKLEFORD Motoo TANAKA Richard J. CARTER Greg SNIDER 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2612-2623
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
random number generator, cellular automata, FPGA, 
 Summary | Full Text:PDF
An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2715-2724
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decomposition, BDDs, logic synthesis, FPGA, 
 Summary | Full Text:PDF
Adaptive Burst M-QAM Modem Architecture for Broadband Wireless Applications
Daniel T. ASPEL David M. KLYMYSHYN 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/12/01
Vol. E85-B  No. 12 ; pp. 2760-2763
Type of Manuscript:  Special Section LETTER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
M-QAM, adaptive modulation, FPGA, software defined radio (SDR), 
 Summary | Full Text:PDF
Configurable and Reconfigurable Computing for Digital Signal Processing
Toshinori SUEYOSHI Masahiro IIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/03/01
Vol. E85-A  No. 3 ; pp. 591-599
Type of Manuscript:  INVITED PAPER (Special Section on the Trend of Digital Signal Processing and Its Future Direction)
Category: LSI/Signal Processors
Keyword: 
configurable computing, reconfigurable computing, digital signal processing, FPGA, 
 Summary | Full Text:PDF
Implementation of a High-Performance Genetic Algorithm Processor for Hardware Optimization
Jinjung KIM Yunho CHOI Chongho LEE Duckjin CHUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/01/01
Vol. E85-C  No. 1 ; pp. 195-203
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
genetic algorithm (GA), FPGA, optimization, 
 Summary | Full Text:PDF
The Kernel-Based Pattern Recognition System Designed by Genetic Algorithms
Moritoshi YASUNAGA Taro NAKAMURA Ikuo YOSHIHARA Jung Hwan KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11 ; pp. 1528-1539
Type of Manuscript:  Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
genetic algorithm, FPGA, pattern recognition, reconfigurable system, kernel-based method, 
 Summary | Full Text:PDF
The Evolutionary Algorithm-Based Reasoning System
Moritoshi YASUNAGA Ikuo YOSHIHARA Jung Hwan KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11 ; pp. 1508-1520
Type of Manuscript:  Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
evolutionary algorithm, reasoning, FPGA, wafer scale integration, fault tolerance, 
 Summary | Full Text:PDF
Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path
Mitsuru YAMADA Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8 ; pp. 1997-2003
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
FIR digital filters, CSD, optimization, integer programming, FPGA, 
 Summary | Full Text:PDF
An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics
Nak-Woong EUM Inhag PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3 ; pp. 829-838
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, routing, routability, delay, 
 Summary | Full Text:PDF
Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs
Hsien-Ho CHUANG Jing-Yang JOU C. Bernard SHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2545-2551
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
technology mapping, FPGA, hard-wired, non-homogeneous, XC4000, 
 Summary | Full Text:PDF
A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath
Akihisa OHTA Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1663-1672
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, bit-serial, logic block architecture, routing architecture, logic utilization, Rent's rule, chip scalability, 
 Summary | Full Text:PDF
Design of DS1 Transport Device in SDH Network
Yeong-Gang SHOW Kuo-Bing CHOU Jim WANG Kou-Tan WU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2000/07/25
Vol. E83-B  No. 7 ; pp. 1389-1399
Type of Manuscript:  PAPER
Category: Fiber-Optic Transmission
Keyword: 
SDH, SONET, DS1, TU-11 mapper, FPGA, 
 Summary | Full Text:PDF
CORDIC-Based Direct Digital Frequency Synthesizer: Comparison with a ROM-Based Architecture in FPGA Implementation
Minkyoung PARK Kiseon KIM Jeong-A LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1282-1285
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
CORDIC, DDFS (Direct Digital Frequency Synthesizer), sine generation, FPGA, 
 Summary | Full Text:PDF
A Study on the Design of VME System Controller
Kang Hyeon RHEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1083-1090
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
factory automaton, VME system controller, VHDL, FPGA, 
 Summary | Full Text:PDF
A Software Antenna: Reconfigurable Adaptive Arrays Based on Eigenvalue Decomposition
Yukihiro KAMIYA Yoshio KARASAWA Satoshi DENNO Yoshihiko MIZUGUCHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1999/12/25
Vol. E82-B  No. 12 ; pp. 2012-2020
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia Mobile Communication Systems)
Category: 
Keyword: 
software antenna, DBF, FPGA, DSP, multipath fading, 
 Summary | Full Text:PDF
Simplified Routing Procedure for a CAD-Verified FPGA
Takahiro MUROOKA Atsushi TAKAHARA Toshiaki MIYAZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2440-2447
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, CAD algorithms, routing, 
 Summary | Full Text:PDF
FPGA-Based Hash Circuit Synthesis with Evolutionary Algorithms
Ernesto DAMIANI Valentino LIBERALI Andrea G. B. TETTAMANZI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9 ; pp. 1888-1896
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
evolvable hardware, evolutionary algorithms, nonlinear circuit synthesis, FPGA, 
 Summary | Full Text:PDF
A Method for Circular Pattern Recognition in a Binary Image and Its Implementation onto an FPGA
Yusuke TOKUNAGA Takahiro INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2 ; pp. 246-254
Type of Manuscript:  Special Section PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
pattern recognition, template matching, digital hardware implementation, FPGA, 
 Summary | Full Text:PDF
200-ps Interchip-Delay Field-Programmable MCM for Telecommunications
Masaru KATAYAMA Takahiro MUROOKA Toshiaki MIYAZAKI Kazuhiro SHIRAKAWA Kazuhiro HAYASHI Takaki ICHIMORI Kennosuke FUKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2673-2678
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, MCM, Interchip delay, 
 Summary | Full Text:PDF
An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications
Nozomu TOGAWA Kayoko HAGI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 873-884
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
FPGA, engineering change, layout reconfiguration, placement and routing, 
 Summary | Full Text:PDF
A Neural-Greedy Combination Algorithm for Board-Level Routing in FPGA-Based Logic Emulation Systems
Nobuo FUNABIKI Junji KITAMICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 866-872
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
FPGA, board-level routing, NP-complete, digital neural network, greedy algorithm, 
 Summary | Full Text:PDF
Routability of FPGAs with Extremal Switch-Block Structures
Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 850-856
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
FPGA, switch-block, routability, detailed-routing, 
 Summary | Full Text:PDF
Computational Complexity Analysis of Set-Bin-Packing Problem
Tomonori IZUMI Toshihiko YOKOMARU Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 842-849
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
bin-packing, complexity, technology mapping, FPGA, 
 Summary | Full Text:PDF
Flexible Hardware Design Methodology for High-Performance ATM Switching System Using Real-Time Emulation Technique
Tsuneo MATSUMURA Naoaki YAMANAKA Ryoichi YAMAGUCHI Keiji ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/02/25
Vol. E81-B  No. 2 ; pp. 466-472
Type of Manuscript:  Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category: Advanced technologies for ATM system
Keyword: 
ATM switching system, LU, emulation, FPGA, interconnect device, 
 Summary | Full Text:PDF
Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map
Kei EGUCHI Takahiro INOUE Akio TSUNEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Vol. E81-C  No. 1 ; pp. 78-81
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
chaos circuits, digital circuits, discrete-time circuits, integrated circuits, FPGA, 
 Summary | Full Text:PDF
A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1795-1806
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, transport processing, layout design, placement and routing, performance optimization, circuit delay, 
 Summary | Full Text:PDF
Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution
Hiroshi SAWADA Takayuki SUYAMA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10 ; pp. 1017-1023
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
FPGA, look-up table (LUT), functional decomposition, Boolean resubstitution, support minimization, 
 Summary | Full Text:PDF
Routability Analysis of Bit-Serial Pipeline Datapaths
Tsuyoshi ISSHIKI Wayne Wei-Ming DAI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1861-1870
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
bit-serial pipeline, Rent's rule, routability, FPGA, 
 Summary | Full Text:PDF
A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs
Tsunemasa HAYASHI Atsushi TAKAHARA Kennosuke FUKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1842-1852
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, telecommunications, multiplexor-type logic cell, BDD-based technology mapping, clustered wiring structure, 
 Summary | Full Text:PDF
Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams
Gueesang LEE Sungju PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1820-1825
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesis, FPGA, Cellular architetcture, Maitra terms, ETDO, 
 Summary | Full Text:PDF
Delay Calculation Method for SRAM-based FPGAs
Masaru KATAYAMA Atsushi TAKAHARA Toshiaki MIYAZAKI Kennosuke FUKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1789-1794
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, propagation delay, CAD, 
 Summary | Full Text:PDF
A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 494-505
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGA, multi-FPGA system, circuit partitioning, path delay, logic-block replication, 
 Summary | Full Text:PDF
Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing
Hideyuki ITO Kouichi NAGAMI Tsunemichi SHIOZAWA Kiyoshi OGURI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 487-493
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
super fine-grain parallel processing, FPGA, high level synthesize PARTHENON, inverter reduction, dynamical system, 
 Summary | Full Text:PDF
Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna
Toyohisa TANAKA Ryu MIURA Yoshio KARASAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/01/25
Vol. E80-B  No. 1 ; pp. 166-175
Type of Manuscript:  PAPER
Category: Antennas and Propagation
Keyword: 
DBF antenna, self-beam-steering, self-phasing, maximal ratio combining, DSP, FPGA, ASIC, 
 Summary | Full Text:PDF
Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout
Nozumu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2140-2150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, transport processing, layout design, placement and routing network flow, 
 Summary | Full Text:PDF
Technology Mapping for FPGAs with Composite Logic Block Architectures
Hsien-Ho CHUANG C. Bernard SHUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1396-1404
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
technology mapping, FPGA, subject graph, pattern graph, 
 Summary | Full Text:PDF
A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 321-329
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGA, technology mapping, layout, path delay, performance optimization, 
 Summary | Full Text:PDF
A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1765-1776
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, circuit partitioning, logic-block replication, network flow, 
 Summary | Full Text:PDF
Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, look up table, technology mapping, layout design, placement, global routing, 
 Summary | Full Text:PDF
Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs
Yoshichika FUJIOKA Michitaka KAMEYAMA Nobuhiro TOMABECHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7 ; pp. 1123-1130
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
delay time, multi-operand multiply-addition, reconfiguration, digital control, FPGA, 
 Summary | Full Text:PDF
Reconfigurable Machine and its Application to Logic Simulation
Nasahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1705-1712
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
reconfigurable machine, logic simulation, FPGA, hardware accelerator, 
 Summary | Full Text:PDF