Keyword : EB tester


EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout
Kazuhiro NOMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1564-1570
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
Keyword: 
EB testerline delay faultfault localizationlayout analysiscombinational circuits
 Summary | Full Text:PDF(296.4KB)

An Analysis of the Economics of the VLSI Development Including Test Cost
Koji NAKAMAE Homare SAKAMOTO Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4 ; pp. 698-705
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
testing and verificationeconomics of VLSI developmenttest costVLSI development cycleEB testerFIB reconstructionfault modeling
 Summary | Full Text:PDF(597.6KB)