Keyword : DVS

Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults
Yukihiro SASAGAWA Jun YAO Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12 ; pp. 3083-3091
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
adaptive redundancy, setup error recovery, DVS, low power, AVF, ILP, 
 Summary | Full Text:PDF
On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
Jinmyoung KIM Toru NAKURA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 560-567
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DVS, fast voltage hopping, resonant supply noise, decoupling capacitor, noise reduction, capacitance boosting, 
 Summary | Full Text:PDF
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path
Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2319-2329
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
adaptive redundancy, setup error recovery, DVS, low power, AVF, 
 Summary | Full Text:PDF
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 511-519
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
power supply noise, resonance, parasitic capacitance, sleep block, DVS, power gating, 
 Summary | Full Text:PDF
Extended MPEG Video Format for Efficient Dynamic Voltage Scaling
Kwanhu BANG Sung-Yong BANG Eui-Young CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/05/01
Vol. E91-A  No. 5 ; pp. 1283-1287
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
low power, energy, DVS, video, decoding, MPEG, 
 Summary | Full Text:PDF
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3634-3641
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
SRAM, DVS, Vth-variation-tolerant, low power, 
 Summary | Full Text:PDF