Keyword : DRAM bandwidth


A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
Jinjia ZHOU Dajiang ZHOU Xun HE Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/08/01
Vol. E93-A  No. 8 ; pp. 1425-1433
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: VLSI Design Technology and CAD
Keyword: 
motion vector derivationDRAM bandwidthultra high resolutionvideo decoderH.264/AVC
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