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A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Rong-Jyi YANG Shen-Iuan LIU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C
No. 8 ;
pp. 1726-1730
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category:
Keyword:
DLL, CDR, dual loop, | | | Summary | Full Text:PDF | |
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A Fast-Lock DLL with Power-On Reset Circuit
Kuo-Hsing CHENG Yu-Lung LO Shu-Yu JIANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A
No. 9 ;
pp. 2210-2220
Type of Manuscript:
Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category:
Keyword:
DLL, PLL, POR, fast lock, multiphase outputs, | | | Summary | Full Text:PDF | |
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A Delay Locked Loop Circuit with Mixed Mode Phase Tuning Technique
Yeo-San SONG Jin-Ku KANG Kwang Sub YOON | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/09/25
Vol. E83-A
No. 9 ;
pp. 1860-1861
Type of Manuscript:
LETTER
Category: Analog Signal Processing
Keyword:
mixed-mode circuit, DLL, Jitter, | | | Summary | Full Text:PDF | |
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A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
Jun-Young PARK Jin-Ku KANG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A
No. 6 ;
pp. 1100-1105
Type of Manuscript:
Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category:
Keyword:
oversampling data recovery, PLL, DLL, jitter, | | | Summary | Full Text:PDF | |
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