Keyword : DLL


Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction
Masahiro KANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA 
Publication:   
Publication Date: 2018/04/01
Vol. E101-C  No. 4 ; pp. 292-298
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
signal integrityresonant power supply noisetriangular active charge injectionDLLvernier TDC
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A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing
Sarang KAZEMINIA Khayrollah HADIDI Abdollah KHOEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 491-496
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
phase shifterfrequency synthesizerfrequency multiplierDLLPLL
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A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption
Kyu-hyoun KIM In-Young CHUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1 ; pp. 208-211
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
second ordercharge pumpphase errorDLLduty cycle corrector (DCC)
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A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Rong-Jyi YANG Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1726-1730
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
DLLCDRdual loop
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A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs
Rong-Jyi YANG Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1248-1252
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
Keyword: 
DLLclock generationwide rangeduty cycle correction
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Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications
In-Young CHUNG Youngsoo SOHN Wonki PARK Changhyun KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 753-759
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DLLjittercounterhysteresiscompensationpower noiseglitch
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A Novel Digitally-Controlled Varactor for Portable Delay Cell Design
Pao-Lung CHEN Ching-Che CHUNG Chen-Yi LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3324-3326
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
portable delay elementdigitally-controlled varactor (DCV)DLLDCOcell-based
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A Fast-Lock DLL with Power-On Reset Circuit
Kuo-Hsing CHENG Yu-Lung LO Shu-Yu JIANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A  No. 9 ; pp. 2210-2220
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
DLLPLLPORfast lockmultiphase outputs
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A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention
Sungkyung PARK Changsik YOO Sin-Chong PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2 ; pp. 505-507
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
four-state dynamic phase detectorharmonic lockingDLL
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A Delay Locked Loop Circuit with Mixed Mode Phase Tuning Technique
Yeo-San SONG Jin-Ku KANG Kwang Sub YOON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/09/25
Vol. E83-A  No. 9 ; pp. 1860-1861
Type of Manuscript:  LETTER
Category: Analog Signal Processing
Keyword: 
mixed-mode circuitDLLJitter
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A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
Jun-Young PARK Jin-Ku KANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1100-1105
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
oversampling data recoveryPLLDLLjitter
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Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface
Yoshinori OKAJIMA Masao TAGUCHI Miki YANAGAWA Koichi NISHIMURA Osamu HAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 798-807
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
DLLsynchronous interfaceDRAMbus timing skew
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