IEICE Trans

Keyword : DFM

Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design Norio SADACHIKA Shu MIMURA Akihiro YUMISAKI Kou JOHGUCHI Akihiro KAYA Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/03/01 Vol. E94-C No. 3 ; pp. 361-367 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: circuit simulation, compact model, DFM, reliability,
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Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing Kokoro KATO Masakazu ENDO Tadao INOUE Shigetoshi NAKATAKE Masaki YAMABE Sunao ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2424-2432 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: Mask Data Rank (MDR), design intent, DFM, MDP,
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Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model Yanming JIA Yici CAI Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3783-3792 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: VLSI, buffer insertion, physical design, DFM, dummy fill,
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Manufacturability-Aware Design of Standard Cells Hirokazu MUTA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 ; pp. 2682-2690 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: manufacturability, variability, DFM, ACLV, standard cell, OPC, RET,
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A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 ; pp. 1919-1926 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: variation-aware, reconfigurable device, FPGA, yield, DFM,
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Proposal of Metrics for SSTA Accuracy Evaluation Hiroyuki KOBAYASHI Nobuto ONO Takashi SATO Jiro IWAI Hidenari NAKASHIMA Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 ; pp. 808-814 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: statistical static timing analysis, statistical max operation, DFM, SoC,
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Fractional Error Estimation Technique of the Space-Based SAR Processor Using RDA In-Pyo HONG Han-Kyu PARK
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2004/04/01 Vol. E87-B No. 4 ; pp. 967-974 Type of Manuscript: PAPER Category: Sensing Keyword: fractional error, DFM, RDA, polynomial DFM model error, azimuth focus error, SAR,
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