Keyword : DDR SDRAM

Cache Optimization for H.264/AVC Motion Compensation
Sangyong YOON Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12 ; pp. 2902-2905
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
cache, H.264, motion compensation, memory bandwidth, DDR SDRAM, 
 Summary | Full Text:PDF
A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Satoru HANZAWA Hiromasa NODA Takeshi SAKATA Osamu NAGASHIMA Sadayuki MORITA Masanori ISODA Michiyo SUZUKI Sadayuki OHKUMA Kyoko MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8 ; pp. 1625-1633
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
clock-recovery circuit, timing adjuster, delay line, DDR SDRAM, 
 Summary | Full Text:PDF