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| Keyword : CDR
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Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network
Yasuhiro TAKE Tadahiro KURODA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C
No. 4 ;
pp. 322-332
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
TCI, Coupled-resonator, 3-D Integration, 3-D clock distribution, CDR, | | | Summary | Full Text:PDF | |
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A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Rong-Jyi YANG Shen-Iuan LIU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C
No. 8 ;
pp. 1726-1730
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category:
Keyword:
DLL, CDR, dual loop, | | | Summary | Full Text:PDF | |
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A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C
No. 6 ;
pp. 956-963
Type of Manuscript:
Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category:
Keyword:
capture range, CCO, CDR, clock and data recovery, false lock, jitter, NRZ, PFD, PLL, VCO, z-domain analysis, | | | Summary | Full Text:PDF | |
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