Keyword : CDFG


High-Level Synthesis with SDRAMs and RAMBUS DRAMs
Asheesh KHARE Preeti R. PANDA Nikil D. DUTT Alexandru NICOLAU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2347-2355
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
schedulingCDFGSDRAMaccess modesmultiple banks
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