Keyword : Boolean network


A Fixed-Parameter Algorithm for Detecting a Singleton Attractor in an AND/OR Boolean Network with Bounded Treewidth
Chia-Jung CHANG Takeyuki TAMURA Kun-Mao CHAO Tatsuya AKUTSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/01/01
Vol. E98-A  No. 1 ; pp. 384-390
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
Boolean networkattractorpartial k-treefixed-parameter algorithm
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On the Complexity of Inference and Completion of Boolean Networks from Given Singleton Attractors
Hao JIANG Takeyuki TAMURA Wai-Ki CHING Tatsuya AKUTSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/11/01
Vol. E96-A  No. 11 ; pp. 2265-2274
Type of Manuscript:  PAPER
Category: General Fundamentals and Boundaries
Keyword: 
Boolean networksingleton attractornetwork completionanother solution problem
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On Finding a Fixed Point in a Boolean Network with Maximum Indegree 2
Tatsuya AKUTSU Takeyuki TAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/08/01
Vol. E92-A  No. 8 ; pp. 1771-1778
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: Theory
Keyword: 
Boolean networkgenetic networkattractorfixed pointboolean satisfiability problem
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Detecting a Singleton Attractor in a Boolean Network Utilizing SAT Algorithms
Takeyuki TAMURA Tatsuya AKUTSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2 ; pp. 493-501
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
Boolean networksingleton attractorfixed pointSATNP-hard
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An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappinglogic minimizationBoolean networkfield-programmable gate array
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