Keyword : Boolean Satisfiability


Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3485-3491
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
exact minimum-width transistor placementBoolean Satisfiabilitynon-dual CMOS cells
 Summary | Full Text:PDF

High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3293-3300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
high speedcell layout synthesisBoolean SatisfiabilitySATCMOS logic cellminimum width
 Summary | Full Text:PDF