Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-ANo. 12 ;
pp. 2463-2471 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: memory BIST, BISR, embedded SRAM, area per good die, iterative improvement algorithm,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-DNo. 10 ;
pp. 1498-1505 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: at-speed test, BISR, embedded DRAM, test cost reduction,
