Keyword : BISR


Reduction of Area per Good Die for SoC Memory Built-In Self-Test
Masayuki ARAI Tatsuro ENDO Kazuhiko IWASAKI Michinobu NAKAO Iwao SUZUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2463-2471
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
memory BISTBISRembedded SRAMarea per good dieiterative improvement algorithm
 Summary | Full Text:PDF

Accomplishment of At-Speed BISR for Embedded DRAMs
Yoshihiro NAGURA Yoshinori FUJIWARA Katsuya FURUE Ryuji OHMURA Tatsunori KOMOIKE Takenori OKITAKA Tetsushi TANIZAKI Katsumi DOSAKA Kazutami ARIMOTO Yukiyoshi KODA Tetsuo TADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1498-1505
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
at-speed testBISRembedded DRAMtest cost reduction
 Summary | Full Text:PDF