IEICE Trans

Keyword : BDD

Revisiting the Top-Down Computation of BDD of Spanning Trees of a Graph and Its Tutte Polynomial Farley Soares OLIVEIRA Hidefumi HIRAISHI Hiroshi IMAI
Publication: Publication Date: 2019/09/01 Vol. E102-A No. 9 ; pp. 1022-1027 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Graph algorithms Keyword: BDD, Tutte polynomial, graph, pathwidth, FPT algorithm,
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Hardness Evaluation for Search LWE Problem Using Progressive BKZ Simulator Yuntao WANG Yoshinori AONO Tsuyoshi TAKAGI
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 ; pp. 2162-2170 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Cryptography and Information Security Keyword: lattice, LWE challenge, BDD, unique SVP, embedding technique, progressive BKZ simulator, post-quantum cryptography,
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Power of Enumeration — Recent Topics on BDD/ZDD-Based Techniques for Discrete Structure Manipulation Shin-ichi MINATO
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 ; pp. 1556-1562 Type of Manuscript: INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Keyword: BDD, ZDD, discrete structure, graph algorithm,
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Techniques of BDD/ZDD: Brief History and Recent Activity Shin-ichi MINATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/07/01 Vol. E96-D No. 7 ; pp. 1419-1429 Type of Manuscript: INVITED SURVEY PAPER Category: Keyword: BDD, ZDD, decision diagram, discrete structure, algorithm, data structure,
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On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating Yu JIN Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2191-2198 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: dynamic power reduction, switching activity reduction, controlling value-based power controlling, BDD,
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Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation Xin MAN Takashi HORIYAMA Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 ; pp. 1347-1358 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: actual power reduction, automatic multi-stage clock gating optimization, ILP formulation, switching activity, BDD, MIP optimizer,
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Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating Xin MAN Takashi HORIYAMA Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2472-2480 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: automatic clock gating generation, low power, dynamic power reduction, BDD,
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A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Yoshifumi KAWAMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 ; pp. 2048-2058 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: embedded system, branching program machine, multi-processing, BDD,
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Fine-Grained Power Gating Based on the Controlling Value of Logic Elements Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3531-3538 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: power gating, multi-threshold CMOS (MTCMOS) technology, BDD, controlling value, leakage power reduction,
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Design of Small RSFQ Microprocessor Based on Cell-Based Top-Down Design Methodology Futabako MATSUZAKI Kenichi YODA Junichi KOSHIYAMA Kei MOTOORI Nobuyuki YOSHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/03/01 Vol. E85-C No. 3 ; pp. 659-664 Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics) Category: Digital Devices and Their Applications Keyword: SFQ, BDD, superconducting circuit, microprocessor, standard cell,
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Computing the Invariant Polynomials of Graphs, Networks and Matroids Hiroshi IMAI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/03/25 Vol. E83-D No. 3 ; pp. 330-343 Type of Manuscript: INVITED SURVEY PAPER Category: Algorithms for Matroids and Related Discrete Systems Keyword: Tutte polynomial, matroid, simplicial complex, network reliability, BDD,
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Computational Investigations of All-Terminal Network Reliability via BDDs Hiroshi IMAI Kyoko SEKINE Keiko IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 ; pp. 714-721 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: network reliability, BDD, output-size sensitive, #P-complete,
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Proposal for Incremental Formal Verification Toru SHONAI Kazuhiko MATSUMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/11/25 Vol. E81-D No. 11 ; pp. 1172-1185 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: formal verification, processor, pipeline, BDD, theorem prover,
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Single-Electron Logic Systems Based on the Binary Decision Diagram Noboru ASAHI Masamichi AKAZAWA Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/25 Vol. E81-C No. 1 ; pp. 49-56 Type of Manuscript: Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices) Category: Keyword: binary decision diagram, BDD, single electron, logic circuit, adder, comparator,
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Counting the Number of Paths in a Graph via BDDs Kyoko SEKINE Hiroshi IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/04/25 Vol. E80-A No. 4 ; pp. 682-688 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: graphs, paths, #P-complete, BDD,
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A Scheduling Method Using Boolean Equations in High-Level Synthesis Toshiaki MIYAZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/12/25 Vol. E75-A No. 12 ; pp. 1728-1731 Type of Manuscript: Special Section LETTER (Special Section on the 1992 IEICE Fall Conference) Category: Keyword: integer linear programming, BDD, data path,
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