Keyword : BCH


Design of q-Parallel LFSR-Based Syndrome Generator
Seung-Youl KIM Kyoung-Rok CHO Je-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 594-596
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
error control codeparallel architectureLFSRBCH
 Summary | Full Text:PDF(450.4KB)

A Processor Accelerator for Software Decoding of BCH Codes
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7 ; pp. 1329-1337
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
error correction codeBCHacceleratorpipelining
 Summary | Full Text:PDF(841.7KB)

Recent Progress in Forward Error Correction for Optical Communication Systems
Takashi MIZUOCHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/05/01
Vol. E88-B  No. 5 ; pp. 1934-1946
Type of Manuscript:  INVITED PAPER (Joint Special Section on Recent Progress in Optoelectronics and Communications)
Category: 
Keyword: 
optical communicationsforward error correctionblock turbo codeReed-SolomonBCHconcatenated codeproduct codeiterative decodingShannon limitcode rate
 Summary | Full Text:PDF(2.2MB)