Keyword : ATPG

A Test Pattern Compaction Method Using SAT-Based Fault Grouping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2302-2309
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ATPG, SAT, test pattern, 
 Summary | Full Text:PDF
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing
Kohei MIYASE Ryota SAKAI Xiaoqing WEN Masao ASO Hiroshi FURUKAWA Yuta YAMATO Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 2003-2011
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
at-speed testing, ATPG, IR-drop, test power reduction, low power test, 
 Summary | Full Text:PDF
Test Pattern Ordering and Selection for High Quality Test Set under Constraints
Michiko INOUE Akira TAKETANI Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12 ; pp. 3001-3009
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small delay defects, SDQL, ATPG, 
 Summary | Full Text:PDF
On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques
Fu-Shing CHIM Tak-Kei LAM Yu-Liang WU Hongbing FAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2853-2865
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design automation, ATPG, implication, redundancy identification, graph-based rewiring, very-large-scale integration, 
 Summary | Full Text:PDF
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
Kohei MIYASE Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Yuta YAMATO Hiroshi FURUKAWA Xiaoqing WEN Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/06/01
Vol. E94-D  No. 6 ; pp. 1216-1226
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
ATPG, X-bit, X-identification, X-filling, 
 Summary | Full Text:PDF
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression
Anis UZZAMAN Brion KELLER Brian FOUTZ Sandeep BHATIA Thomas BARTENSTEIN Masayuki ARAI Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1 ; pp. 17-23
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
test compression, hybrid compression, volume diagnosis, ATPG, partial good chip, 
 Summary | Full Text:PDF
Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI Tatsuru MATSUO Takahisa HIRAIDE Hideaki KONISHI Michiaki EMORI Takashi AIKYO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 726-735
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Test Compression
Keyword: 
test data compression, test response compaction, BIST-aided scan test, X-value, ATPG, 
 Summary | Full Text:PDF
Multi-Cycle Path Detection for Sequential Circuits and Its Application to Real Designs
Hiroyuki HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3176-3183
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
multi-cycle path, false path, sequential circuit, implication, ATPG, multiple clock, 
 Summary | Full Text:PDF
High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph
Eunjung OH Soo-Hyun KIM Dong-Ik LEE Ho-Yong CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2674-2683
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test Generation
Keyword: 
asynchronous circuits, ATPG, STG, 
 Summary | Full Text:PDF
Average Power Reduction in Scan Testing by Test Vector Modification
Seiji KAJIHARA Koji ISHIDA Kohei MIYASE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1483-1489
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
Keyword: 
test power reduction, scan testing, ATPG, test modification, 
 Summary | Full Text:PDF
Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification
Eunjung OH Jeong-Gun LEE Dong-Ik LEE Ho-Yong CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6 ; pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
ATPG, SI asynchronous circuits, signal transition graph, testing, 
 Summary | Full Text:PDF
An Iterative Improvement Method for Generating Compact Tests for IDDQ Testing of Bridging Faults
Tsuyoshi SHINOGI Terumine HAYASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 682-688
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
compaction, IDDQ testing, iterative improvement method, bridging fault, ATPG, 
 Summary | Full Text:PDF