IEICE Trans

Keyword : ASIP

HOG-Based Object Detection Processor Design Using ASIP Methodology Shanlin XIAO Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2972-2984 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ASIP, histogram of oriented gradients (HOG), embedded processor, computer vision, object detection,
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Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm Shanlin XIAO Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 ; pp. 1384-1395 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: ASIP, embedded processor, computer vision, object detection, AdaBoost,
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A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 ; pp. 1222-1235 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: ASIP, image processing,
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A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing Hsuan-Chun LIAO Mochamad ASRI Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2373-2383 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: ASIP, image processing,
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Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm Yuli ZHANG Jun HAN Xinqian WENG Zhongzhu HE Xiaoyang ZENG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/08/01 Vol. E95-C No. 8 ; pp. 1415-1426 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SHA-3, BLAKE algorithm, ISE, ASIP,
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A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: pressure sensing, urinary bladder, SoC, low power, ASIP,
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Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 ; pp. 2283-2294 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: application partitioning, CAD algorithm, MPSoC, ASIP, synthesis,
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Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 ; pp. 2456-2464 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Electronic Circuits and Systems Keyword: hardware/software partitioning, CAD algorithm, search space smoothing, MPSoC, ASIP,
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A Partial Access Mechanism on a Register for Low-Cost Embedded Multimedia ASIP Ha-young JEONG Min-young CHO Won HUR Yong-surk LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/07/01 Vol. E91-C No. 7 ; pp. 1171-1174 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: embedded processor, ASIP, SIMD, partial access,
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A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors Shinsuke KOBAYASHI Kentaro MITA Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2586-2595 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: compiler generation, ASIP, design space exploration,
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An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes Nguyen Ngoc BINH Masaharu IMAI Yoshinori TAKEUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 ; pp. 2612-2620 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design Keyword: ASIP, HW/SW partitioning, performance estimation, RAM, ROM,
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A New Approach for Datapath Synthesis of Application Specific Instruction Processor Kyung-Sik JANG Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/08/25 Vol. E80-A No. 8 ; pp. 1478-1488 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ASIP, datapath synthesis, architecture synthesis,
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An Instruction Set Optimization Algorithm for Pipelined ASIPs Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 ; pp. 1707-1714 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: ASIP, pipelined architecture, HW/SW partitioning, performance estimation, PEAS-I system,
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An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI Yoshimichi HONMA Jun SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 ; pp. 353-362 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: scheduling, pipeline hazards, HW/SW partitioning, ASIP, performance estimation, PEAS-I system,
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PEAS-I： A Hardware/Software Codesign System for ASIP Development Jun SATO Alauddin Y. ALOMARY Yoshimichi HONMA Takeharu NAKATA Akichika SHIOMI Nobuyuki HIKICHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/03/25 Vol. E77-A No. 3 ; pp. 483-491 Type of Manuscript: Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems) Category: Computer Aided Design (CAD) Keyword: ASIP, hardware/software codesign, PEAS-I, CPU core design automation, application program development tool generation,
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An Integer Programming Approach to Instruction Set Selection Problem Alauddin Y. ALOMARY Masaharu IMAI Jun SATO Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 ; pp. 1849-1857 Type of Manuscript: PAPER Category: VLSI Design Technology Keyword: ASIP, VLSI CAD, instruction set optimization, branch-and-bound method,
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An ASIP Instruction Set Optimization Algorithm with Functional Module Sharing Constraint Alauddin Y. ALOMARY Masaharu IMAI Nobuyuki HIKICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 ; pp. 1713-1720 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: ASIP, instruction set optimization, branch-and-bound method, functional module sharing, PEAS system,
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