Keyword : ASIC


An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field
Hiromitsu AWANO Tadayuki ICHIHASHI Makoto IKEDA 
Publication:   
Publication Date: 2019/01/01
Vol. E102-A  No. 1 ; pp. 56-64
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
pairing based cryptographyhardware securityASICoptimal-ate pairinginstruction scheduling optimization
 Summary | Full Text:PDF(2.7MB)

Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor
Shotaro SUGIYAMA Hiromitsu AWANO Makoto IKEDA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2290-2296
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ECDSAV2X communicationHardware securityASICscalar multiplication
 Summary | Full Text:PDF(1.9MB)

A Robust Speech Communication into Smart Info-Media System
Yoshikazu MIYANAGA Wataru TAKAHASHI Shingo YOSHIZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/11/01
Vol. E96-A  No. 11 ; pp. 2074-2080
Type of Manuscript:  INVITED PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: 
Keyword: 
smart info-media systemrobust speech recognitionvoice activity detectionspeech rejectionASIClow power consumption design
 Summary | Full Text:PDF(1.4MB)

Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process
Duc-Hung LE Katsumi INOUE Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/09/01
Vol. E96-A  No. 9 ; pp. 1883-1888
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
FPGAASICmatching systemContent Addressable Memory (CAM)multi-matchexact pattern matching
 Summary | Full Text:PDF(651.7KB)

An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation
Minoru IIZUKA Naohiro HAMADA Hiroshi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 482-491
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuits with bundled-data implementationlatencyASICand design support tool
 Summary | Full Text:PDF(1.6MB)

Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2628-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
block cipherKASUMIhardwareASICFPGAcompact implementation
 Summary | Full Text:PDF(945.4KB)

Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture
Cao LIANG Xinming HUANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 407-415
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
coarse-grained reconfigurable architectureparallel FFTenergy efficiencyASICFPGADSP
 Summary | Full Text:PDF(758.6KB)

Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
Dai YAMAMOTO Jun YAJIMA Kouichi ITOH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A  No. 1 ; pp. 3-12
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Symmetric Cryptography
Keyword: 
block cipherMISTY1hardwareASICcompact implementation
 Summary | Full Text:PDF(599.3KB)

Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption
Nozomi ISHIHARA Koki ABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8 ; pp. 2068-2075
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
DWTsignal processingparallel architectureefficient memory accessburst accessASIC
 Summary | Full Text:PDF(499.3KB)

The Design of a Monolithic MSTP ASIC
Peng WANG Chao ZHANG Nan HUA De-peng JIN Lie-guang ZENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/08/01
Vol. E89-C  No. 8 ; pp. 1248-1254
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
MSTPASICERSTHLB
 Summary | Full Text:PDF(795.7KB)

A Method to Derive SSO Design Rule Considering Jitter Constraint
Koutaro HACHIYA Hiroyuki KOBAYASHI Takaaki OKUMURA Takashi SATO Hiroki OKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 865-872
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
simultaneous switching outputsimultaneous switching noisejitterASIC
 Summary | Full Text:PDF(437.5KB)

Hardware Design Verification Using Signal Transitions and Transactions
Nobuyuki OHBA Kohji TAKANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 1012-1017
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
hardware prototypinghardware debugginglogic analyzerASICSoC
 Summary | Full Text:PDF(664.1KB)

A Design for Testability Technique for Low Power Delay Fault Testing
James Chien-Mo LI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 621-628
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
testability technology (design for testability)delay fault testinglow powerASIC
 Summary | Full Text:PDF(1.2MB)

A New Implementation Technique to Decode the Convolutional Code in Trellis-Coded Modulation
Anh DINH Xiao HU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 619-627
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
TCMlook-up-tableViterbi decodingIP coreASICVLSI architecture
 Summary | Full Text:PDF(1.3MB)

A Systolic Array RLS Processor
Takahiro ASAI Tadashi MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2001/05/01
Vol. E84-B  No. 5 ; pp. 1356-1361
Type of Manuscript:  PAPER
Category: Terrestrial Radio Communications
Keyword: 
RLS algorithmchannel estimationQR decompositionparallel pipelined processingASIC
 Summary | Full Text:PDF(758.6KB)

Hardware Implementation of the High-Dimensional Discrete Torus Knot Code
Yuuichi HAMASUNA Masanori YAMAMURA Toshio ISHIZAKA Masaaki MATSUO Masayasu HATA Ichi TAKUMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/04/01
Vol. E84-A  No. 4 ; pp. 949-956
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals of Information and Communications)
Category: 
Keyword: 
robust and high speed error correctionburst errorwired logic and parallel operationASIC
 Summary | Full Text:PDF(1.4MB)

Low-Power Architectures for Programmable Multimedia Processors
Takao NISHITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2 ; pp. 184-196
Type of Manuscript:  INVITED PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
multimedia processorsSOCASICMPUDSP
 Summary | Full Text:PDF(886.9KB)

A Reconfigurable Digital Signal Processor
Boon Keat TAN Toru OGAWA Ryuji YOSHIMURA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1424-1430
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DSP processorreconfigurableflexibleprocessors arrayfault-tolerantASICdigital signal processingRISC
 Summary | Full Text:PDF(739.3KB)

Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna
Toyohisa TANAKA Ryu MIURA Yoshio KARASAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/01/25
Vol. E80-B  No. 1 ; pp. 166-175
Type of Manuscript:  PAPER
Category: Antennas and Propagation
Keyword: 
DBF antennaself-beam-steeringself-phasingmaximal ratio combiningDSPFPGAASIC
 Summary | Full Text:PDF(901.5KB)

An ASIC Implementation Scheme to Realize a Beam Space CMA Adaptive Array Antenna
Toyohisa TANAKA Ryu MIURA Isamu CHIBA Yoshio KARASAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1995/11/25
Vol. E78-B  No. 11 ; pp. 1467-1473
Type of Manuscript:  Special Section PAPER (Special Issue on Adaptive Signal Processing Technology in Antennas)
Category: 
Keyword: 
adaptive antennaDBF antennaCMADSPASIC
 Summary | Full Text:PDF(583.7KB)

A Flexible and Low-Cost ASIC Line Management Technology Taking Operator's Skill-Level as a Scheduling-Factor into Consideration
Tetsuma SAKURAI Satoshi TAZAWA Eisuke ARAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C  No. 3 ; pp. 236-240
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
ASICmanufacturingfabricationline managementTAToperatorshiftlow cost
 Summary | Full Text:PDF(442.2KB)

A Scalable and Flexible CIM System with Precise and Quick Scheduler for ASIC
Kou WADA Tsuneo OKUBO Satoshi TAZAWA Tetsuma SAKURAI Eisuke ARAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C  No. 3 ; pp. 229-235
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
integrated electronicsinstrumentation and controlCIMASICFA
 Summary | Full Text:PDF(623.8KB)

An On-Line Scheduler for ASIC Manufacturing Line Management
Tadao TAKEDA Satoshi TAZAWA Kou WADA Eisuke ARAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/03/25
Vol. E78-C  No. 3 ; pp. 241-247
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies)
Category: 
Keyword: 
schedulerASICTATalgorithm
 Summary | Full Text:PDF(676.9KB)

ASIC Approaches for Vision-Based Vehicle Guidance
Ichiro MASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1735-1743
Type of Manuscript:  INVITED PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
ASICstereo visionintelligent vehiclesprocessor architecture
 Summary | Full Text:PDF(924.8KB)

A Fuzzy Inference LSI for an Automotive Control
Yoshihisa HARATA Norikazu OHTA Kiyoharu HAYAKAWA Takashi SHIGEMATSU Yasushi KITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1780-1787
Type of Manuscript:  Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
ASICcar-electronicsfuzzyreal-time control
 Summary | Full Text:PDF(930KB)

Multiplexing and Data Communications Integrated Circuits for Automotive In-Vehicle Networks
Akira KAWAHASHI Masaki AZUMA Yasushi SHINOJIMA Masaru NAGAO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1756-1766
Type of Manuscript:  Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
automotive electronicsmultiplexingdata communicationsASIC
 Summary | Full Text:PDF(1.2MB)

In-Vehicle Information Systems and Semiconductor Devices They Employ
Takeshi INOUE Kikuo MURAMATSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1744-1755
Type of Manuscript:  INVITED PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
in-vehicle information systemnavigation systemvehicle positioningroute planningroute guidancemap databaseASICgraphic display controller
 Summary | Full Text:PDF(1.1MB)

The Role of ASICs in Automotive Control Systems
Koichi MURAKAMI Takeshi FUJISHIRO Ken ITO Yoshitaka HATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1727-1734
Type of Manuscript:  INVITED PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
ASICautomotive control systemsengine control systemschassis control systems
 Summary | Full Text:PDF(634.6KB)

High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1641-1648
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
ASICCMOSmacrocellmemoryconfigurablerow sliceabledecodershort design Turn-Around-Time (TAT)
 Summary | Full Text:PDF(692.2KB)

A Programmable Parallel Digital Neurocomputer
Yoshiyuki SHIMOKAWA Yutaka FUWA Naruhiko ARAMAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1197-1205
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural networkneurocomputerneuro chipASIC
 Summary | Full Text:PDF(890.9KB)