IEICE Trans

Keyword : ASIC

An ASIC Crypto Processor for 254-Bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field Hiromitsu AWANO Tadayuki ICHIHASHI Makoto IKEDA
Publication: Publication Date: 2019/01/01 Vol. E102-A No. 1 ; pp. 56-64 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Keyword: pairing based cryptography, hardware security, ASIC, optimal-ate pairing, instruction scheduling optimization,
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Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor Shotaro SUGIYAMA Hiromitsu AWANO Makoto IKEDA
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 ; pp. 2290-2296 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: ECDSA, V2X communication, Hardware security, ASIC, scalar multiplication,
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A Robust Speech Communication into Smart Info-Media System Yoshikazu MIYANAGA Wataru TAKAHASHI Shingo YOSHIZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/11/01 Vol. E96-A No. 11 ; pp. 2074-2080 Type of Manuscript: INVITED PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Keyword: smart info-media system, robust speech recognition, voice activity detection, speech rejection, ASIC, low power consumption design,
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Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process Duc-Hung LE Katsumi INOUE Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/09/01 Vol. E96-A No. 9 ; pp. 1883-1888 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: FPGA, ASIC, matching system, Content Addressable Memory (CAM), multi-match, exact pattern matching,
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An ASIC Design Support Tool Set for Non-pipelined Asynchronous Circuits with Bundled-Data Implementation Minoru IIZUKA Naohiro HAMADA Hiroshi SAITO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 ; pp. 482-491 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: asynchronous circuits with bundled-data implementation, latency, ASIC, and design support tool,
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Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher Dai YAMAMOTO Kouichi ITOH Jun YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2628-2638 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation,
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Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture Cao LIANG Xinming HUANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 ; pp. 407-415 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: coarse-grained reconfigurable architecture, parallel FFT, energy efficiency, ASIC, FPGA, DSP,
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Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher Dai YAMAMOTO Jun YAJIMA Kouichi ITOH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/01/01 Vol. E93-A No. 1 ; pp. 3-12 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Symmetric Cryptography Keyword: block cipher, MISTY1, hardware, ASIC, compact implementation,
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Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption Nozomi ISHIHARA Koki ABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 ; pp. 2068-2075 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: DWT, signal processing, parallel architecture, efficient memory access, burst access, ASIC,
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The Design of a Monolithic MSTP ASIC Peng WANG Chao ZHANG Nan HUA De-peng JIN Lie-guang ZENG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/08/01 Vol. E89-C No. 8 ; pp. 1248-1254 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: MSTP, ASIC, ERST, HLB,
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A Method to Derive SSO Design Rule Considering Jitter Constraint Koutaro HACHIYA Hiroyuki KOBAYASHI Takaaki OKUMURA Takashi SATO Hiroki OKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 ; pp. 865-872 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: simultaneous switching output, simultaneous switching noise, jitter, ASIC,
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Hardware Design Verification Using Signal Transitions and Transactions Nobuyuki OHBA Kohji TAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 ; pp. 1012-1017 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware prototyping, hardware debugging, logic analyzer, ASIC, SoC,
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A Design for Testability Technique for Low Power Delay Fault Testing James Chien-Mo LI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 ; pp. 621-628 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: testability technology (design for testability), delay fault testing, low power, ASIC,
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A New Implementation Technique to Decode the Convolutional Code in Trellis-Coded Modulation Anh DINH Xiao HU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/03/01 Vol. E87-A No. 3 ; pp. 619-627 Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing) Category: Communication Theory and Systems Keyword: TCM, look-up-table, Viterbi decoding, IP core, ASIC, VLSI architecture,
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A Systolic Array RLS Processor Takahiro ASAI Tadashi MATSUMOTO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2001/05/01 Vol. E84-B No. 5 ; pp. 1356-1361 Type of Manuscript: PAPER Category: Terrestrial Radio Communications Keyword: RLS algorithm, channel estimation, QR decomposition, parallel pipelined processing, ASIC,
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Hardware Implementation of the High-Dimensional Discrete Torus Knot Code Yuuichi HAMASUNA Masanori YAMAMURA Toshio ISHIZAKA Masaaki MATSUO Masayasu HATA Ichi TAKUMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/04/01 Vol. E84-A No. 4 ; pp. 949-956 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals of Information and Communications) Category: Keyword: robust and high speed error correction, burst error, wired logic and parallel operation, ASIC,
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Low-Power Architectures for Programmable Multimedia Processors Takao NISHITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 ; pp. 184-196 Type of Manuscript: INVITED PAPER (Special Section on VLSI for Digital Signal Processing) Category: Keyword: multimedia processors, SOC, ASIC, MPU, DSP,
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A Reconfigurable Digital Signal Processor Boon Keat TAN Toru OGAWA Ryuji YOSHIMURA Kenji TANIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 ; pp. 1424-1430 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: DSP processor, reconfigurable, flexible, processors array, fault-tolerant, ASIC, digital signal processing, RISC,
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Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna Toyohisa TANAKA Ryu MIURA Yoshio KARASAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1997/01/25 Vol. E80-B No. 1 ; pp. 166-175 Type of Manuscript: PAPER Category: Antennas and Propagation Keyword: DBF antenna, self-beam-steering, self-phasing, maximal ratio combining, DSP, FPGA, ASIC,
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An ASIC Implementation Scheme to Realize a Beam Space CMA Adaptive Array Antenna Toyohisa TANAKA Ryu MIURA Isamu CHIBA Yoshio KARASAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1995/11/25 Vol. E78-B No. 11 ; pp. 1467-1473 Type of Manuscript: Special Section PAPER (Special Issue on Adaptive Signal Processing Technology in Antennas) Category: Keyword: adaptive antenna, DBF antenna, CMA, DSP, ASIC,
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A Flexible and Low-Cost ASIC Line Management Technology Taking Operator's Skill-Level as a Scheduling-Factor into Consideration Tetsuma SAKURAI Satoshi TAZAWA Eisuke ARAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/03/25 Vol. E78-C No. 3 ; pp. 236-240 Type of Manuscript: Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies) Category: Keyword: ASIC, manufacturing, fabrication, line management, TAT, operator, shift, low cost,
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A Scalable and Flexible CIM System with Precise and Quick Scheduler for ASIC Kou WADA Tsuneo OKUBO Satoshi TAZAWA Tetsuma SAKURAI Eisuke ARAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/03/25 Vol. E78-C No. 3 ; pp. 229-235 Type of Manuscript: Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies) Category: Keyword: integrated electronics, instrumentation and control, CIM, ASIC, FA,
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An On-Line Scheduler for ASIC Manufacturing Line Management Tadao TAKEDA Satoshi TAZAWA Kou WADA Eisuke ARAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/03/25 Vol. E78-C No. 3 ; pp. 241-247 Type of Manuscript: Special Section PAPER (Special Issue on Sub-1/4 Micron Device and Process Technologies) Category: Keyword: scheduler, ASIC, TAT, algorithm,
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ASIC Approaches for Vision-Based Vehicle Guidance Ichiro MASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1735-1743 Type of Manuscript: INVITED PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: ASIC, stereo vision, intelligent vehicles, processor architecture,
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A Fuzzy Inference LSI for an Automotive Control Yoshihisa HARATA Norikazu OHTA Kiyoharu HAYAKAWA Takashi SHIGEMATSU Yasushi KITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1780-1787 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: ASIC, car-electronics, fuzzy, real-time control,
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Multiplexing and Data Communications Integrated Circuits for Automotive In-Vehicle Networks Akira KAWAHASHI Masaki AZUMA Yasushi SHINOJIMA Masaru NAGAO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1756-1766 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: automotive electronics, multiplexing, data communications, ASIC,
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In-Vehicle Information Systems and Semiconductor Devices They Employ Takeshi INOUE Kikuo MURAMATSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1744-1755 Type of Manuscript: INVITED PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: in-vehicle information system, navigation system, vehicle positioning, route planning, route guidance, map database, ASIC, graphic display controller,
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The Role of ASICs in Automotive Control Systems Koichi MURAKAMI Takeshi FUJISHIRO Ken ITO Yoshitaka HATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1727-1734 Type of Manuscript: INVITED PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: ASIC, automotive control systems, engine control systems, chassis control systems,
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High-Performance Memory Macrocells with Row and Column Sliceable Architecture Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 ; pp. 1641-1648 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: ASIC, CMOS, macrocell, memory, configurable, row sliceable, decoder, short design Turn-Around-Time (TAT),
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A Programmable Parallel Digital Neurocomputer Yoshiyuki SHIMOKAWA Yutaka FUWA Naruhiko ARAMAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 ; pp. 1197-1205 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Neural Networks and Chips Keyword: neural network, neurocomputer, neuro chip, ASIC,
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