Keyword : 1 1/2 track-switch model

An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/08/25
Vol. E83-D  No. 8 ; pp. 1701-1705
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
fault tolerant processor arrays, 1 1/2 track-switch model, self-reconfigurable system, run-time fault tolerance, wafer scale integration, 
 Summary | Full Text:PDF(662.1KB)
An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12 ; pp. 1545-1553
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
mesh-connected parallel computer, wafer scale integration, yield enhancement, fault tolerance, 1 1/2 track-switch model, 
 Summary | Full Text:PDF(962.4KB)