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IEICE TRANSACTIONS on Information and Systems
Volume E85-D No.10  (Publication Date:2002/10/01)
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Special Issue on Test and Verification of VLSI

pp.1465-1465  FOREWORD
FOREWORD
Hiromi HIRAISHI  
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pp.1466-1473  PAPER-Test Generation and Modification
Test Generation for Test Compression Based on Statistical Coding
Hideyuki ICHIHARA  Atsuhiro OGAWA  Tomoo INOUE  Akio TAMURA  
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pp.1474-1482  PAPER-Test Generation and Modification
Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits
Toshinori HOSOKAWA  Hiroshi DATE  Michiaki MURAOKA  
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pp.1483-1489  PAPER-Test Generation and Modification
Average Power Reduction in Scan Testing by Test Vector Modification
Seiji KAJIHARA  Koji ISHIDA  Kohei MIYASE  
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pp.1490-1497  PAPER-BIST
Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
Kenichi ICHINO  Takeshi ASAKAWA  Satoshi FUKUMOTO  Kazuhiko IWASAKI  Seiji KAJIHARA  
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pp.1498-1505  PAPER-BIST
Accomplishment of At-Speed BISR for Embedded DRAMs
Yoshihiro NAGURA  Yoshinori FUJIWARA  Katsuya FURUE  Ryuji OHMURA  Tatsunori KOMOIKE  Takenori OKITAKA  Tetsushi TANIZAKI  Katsumi DOSAKA  Kazutami ARIMOTO  Yukiyoshi KODA  Tetsuo TADA  
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pp.1506-1514  PAPER-Test and Diagnosis for Timing Faults
High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO  Yoshikazu KIYOSHIGE  Yasuo SATO  Kazumi HATAYAMA  Satoshi FUKUMOTO  Kazuhiko IWASAKI  
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pp.1515-1525  PAPER-Test and Diagnosis for Timing Faults
Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI  Marong PHADOONGSIDHI  Yoshinobu HIGAMI  Kewal K. SALUJA  Yuzo TAKAMATSU  
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pp.1526-1533  PAPER-Test and Diagnosis for Timing Faults
Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits
Kazuya SHIMIZU  Takanori SHIRAI  Masaya TAKAMURA  Noriyoshi ITAZAKI  Kozo KINOSHITA  
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pp.1534-1541  PAPER-Current Test
IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
Masaki HASHIZUME  Teppei TAKEDA  Masahiro ICHIMIYA  Hiroyuki YOTSUYANAGI  Yukiya MIURA  Kozo KINOSHITA  
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pp.1542-1550  PAPER-Current Test
CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply
Masaki HASHIZUME  Masahiro ICHIMIYA  Hiroyuki YOTSUYANAGI  Takeomi TAMESADA  
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pp.1551-1557  PAPER-Analog/Mixed Signal Test
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model
Yukiya MIURA  
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pp.1558-1563  PAPER-EB Tester
EB-Testing-Pad Method and its Evaluation by Actual Devices
Norio KUJI  Takako ISHIHARA  Shigeru NAKAJIMA  
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pp.1564-1570  PAPER-EB Tester
EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout
Kazuhiro NOMURA  Koji NAKAMAE  Hiromu FUJIOKA  
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pp.1571-1578  PAPER-Debugging Multiple Processors
A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication
Noriyuki MINEGISHI  Ken-ichi ASANO  Hirokazu SUZUKI  Keisuke OKADA  Takashi KAN  
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pp.1579-1586  PAPER-Verification
Symbolic Model Checking of Deadlock Free Property of Task Control Architecture
Hiromi HIRAISHI  
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pp.1587-1594  PAPER-Verification
Verifying Signal-Transition Consistency of High-Level Designs Based on Symbolic Simulation
Kiyoharu HAMAGUCHI  Hidekazu URUSHIHARA  Toshinobu KASHIWABARA  
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pp.1595-1604  PAPER-Verification
Framework of Timed Trace Theoretic Verification Revisited
Bin ZHOU  Tomohiro YONEDA  Chris MYERS  
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pp.1605-1608  LETTER
Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States
Hiroyuki YOTSUYANAGI  Masaki HASHIZUME  Takeomi TAMESADA  
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Regular Section

pp.1609-1618  PAPER-Computer Systems
Hybrid Schemes and Variable-Size Subblock TLBs: Aggressive Superpage Supports
Cheol Ho PARK  Daeyeon PARK  
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pp.1619-1627  PAPER-Software Systems
Arranging and Clustering Results of Information Filtering for Effective Conceptual Browsing
Yanhua QU  Makoto NAKASHIMA  Tetsuro ITO  
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pp.1628-1635  PAPER-Databases
Minimizing Up-Front Data Transmission on Web Based Vector GIS
Young-Hwan OH  Hae-Young BAE  
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pp.1636-1644  PAPER-Network
FLASH: Fast and Scalable Table-Lookup Engine Architecture for Telecommunications
Tsunemasa HAYASHI  Toshiaki MIYAZAKI  
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pp.1645-1653  PAPER-Artificial Intelligence, Cognitive Science
Proof for the Equivalence between Some Best-First Algorithms and Depth-First Algorithms for AND/OR Trees
Ayumu NAGAI  Hiroshi IMAI  
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pp.1654-1662  PAPER-Image Processing, Image Pattern Recognition
Robust Face Detection Using a Modified Radial Basis Function Network
LinLin HUANG  Akinobu SHIMIZU  Yoshihiro HAGIHARA  Hidefumi KOBATAKE  
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pp.1663-1677  PAPER-Computer Graphics
Wrinkly Surface Generated on Irregular Mesh by Using IST Generalized on Code Space and Multi-Dimensional Space: Unification of Interpolation Surface and Fractal
Tadahiro FUJIMOTO  Yoshio OHNO  Kazunobu MURAOKA  Norishige CHIBA  
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pp.1678-1687  PAPER-Multimedia Pattern Processing
Recognition of Shape-Changing Hand Gestures
Mun-Ho JEONG  Yoshinori KUNO  Nobutaka SHIMADA  Yoshiaki SHIRAI  
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pp.1688-1697  PAPER-Natural Language Processing
Disambiguating Word Senses in Korean-Japanese Machine Translation by Using Semi-Automatically Constructed Ontology
Sin-Jae KANG  You-Jin CHUNG  Jong-Hyeok LEE  
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pp.1698-1709  PAPER-Medical Engineering
Automatic Segmentation of a Brain Region in MR Images Using Automatic Thresholding and 3D Morphological Operations
Tae-Woo KIM  Dong-Uk CHO  
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pp.1710-1718  PAPER-Medical Engineering
Neural Filter with Selection of Input Features and Its Application to Image Quality Improvement of Medical Image Sequences
Kenji SUZUKI  Isao HORIBA  Noboru SUGIE  Michio NANKI  
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pp.1719-1722  LETTER-Applications of Information Security Techniques
A Novel Cryptosystem with Lock Generation and Sum-Difference Replacement Ladder
Victor R. L. SHEN  Tzer-Shyong CHEN  
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pp.1723-1726  LETTER-Image Processing, Image Pattern Recognition
Image Coding Using Wavelet-Based Fractal Approximation
Sang Hyun KIM  Ick Hoon JANG  Nam Chul KIM  
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