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IEICE TRANSACTIONS on Information and Systems
Volume E78-D No.7  (Publication Date:1995/07/25)
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Special Issue on Verification, Test and Diagnosis of VLSI Systems

pp.789-790  FOREWORD
FOREWORD
Hideo FUJIWARA  
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pp.791-795  PAPER
Towards Verification of Bit-Slice Circuits--Time-Space Modal Model Checking Approach--
Hiromi HIRAISHI  
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pp.796-801  PAPER
Temporal Verification of Real-Time Systems
Sérgio V. CAMPOS  Edmund M. CLARKE  Wilfredo MARRERO  Marius MINEA  Hiromi HIRAISHI  
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pp.802-810  PAPER
A New Conformance Testing Technique for Localization of Multiple Faults in Communication Protocols
Yoshiaki KAKUDA  Hideki YUKITOMO  Shinji KUSUMOTO  Tohru KIKUNO  
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pp.811-816  PAPER
Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Seiji KAJIHARA  Rikiya NISHIGAYA  Tetsuji SUMIOKA  Kozo KINOSHITA  
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pp.817-821  PAPER
A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Koji YAMAZAKI  Teruhiko YAMADA  
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pp.822-829  PAPER
A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
Xiangqiu YU  Hiroshi TAKAHASHI  Yuzo TAKAMATSU  
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pp.830-838  PAPER
Testing of k-FR Circuits under Highly Observable Condition
Xiaoqing WEN  Hideo TAMAMOTO  Kozo KINOSHITA  
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pp.839-844  PAPER
The Effect of CMOS VLSI IDDq Measurement on Defect Level
Junichi HIRASE  Masanori HAMADA  
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pp.845-852  PAPER
A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs
Yukiya MIURA  Sachio NAITO  
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pp.853-860  PAPER
Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit
Shigeharu TESHIMA  Naoya CHUJO  Ryuta TERASHIMA  
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pp.861-867  PAPER
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI  Seiji KAJIHARA  Kozo KINOSHITA  
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pp.868-873  PAPER
A Practical Test System with a Fuzzy Logic Controller
Takeshi KOYAMA  Ryuji OHMURA  
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pp.874-881  PAPER
The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs
Tokumi YOKOHIRA  Toshimi SHIMIZU  Hiroyuki MICHINISHI  Yuji SUGIYAMA  Takuji OKAMOTO  
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pp.882-888  PAPER
Design of Autonomous TPG Circuits for Use in Two-Pattern Testing
Kiyoshi FURUYA  Seiji SEKI  Edward J. McCLUSKEY  
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pp.889-894  PAPER
Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing
Kiyoshi FURUYA  Susumu YAMAZAKI  Masayuki SATO  
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Regular Section

pp.895-900  PAPER-Automata, Languages and Theory of Computing
The Firing Squad Synchronization Problem in Defective Cellular Automata
Martin KUTRIB  Roland VOLLMAR  
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pp.901-908  PAPER-Algorithm and Computational Complexity
The Complexity of Drawing Tree-Structured Diagrams
Kensei TSUCHIDA  
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pp.909-916  PAPER-Image Processing, Computer Graphics and Pattern Recognition
Global Interpolation in the Segmentation of Handwritten Characters Overlapping a Border
Satoshi NAOI  Maki YABUKI  Atsuko ASAKAWA  Yoshinobu HOTTA  
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pp.917-922  PAPER-Image Processing, Computer Graphics and Pattern Recognition
Direct Reconstruction of Planar Surfaces by Stereo Vision
Yasushi KANAZAWA  Kenichi KANATANI  
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