C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)

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Online ISSN : 1881-0217
Volume J96-C No.11  (Publication Date:2013/11/01)
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Special Issue on 3D Chip Stacking and Advanced Design/Evaluation Technologies for Future Electronic Packaging

pp.311-318  PAPER  Open Access Paper
Developing “Functionally Innovative Three-Dimensional Integrated Circuit (Dream Chip)” Technology by ASET
Hiroaki IKEDA  
Summary | FreeFull Text(in Japanese):PDF(3.7MB)

pp.319-326  PAPER  Open Access Paper
Present State of Three Dimensional Packaging Technology Using Through Silicon Via
Sei-ichi DENDA  
Summary | FreeFull Text(in Japanese):PDF(1.7MB)

pp.327-334  PAPER  Open Access Paper
Jisso Technology of the Ultra-Low Height Camera Module Corresponding to the Thin Trend of Smartphone
Hironori NAKAJO  
Summary | FreeFull Text(in Japanese):PDF(2.8MB)

pp.335-343  PAPER
Chip-level TSV Process for Development of 3D System LSIs
Kazuyuki HOZAWA  Futoshi FURUTA  Yuko HANAOKA  Mayu AOKI  Kenichi OSADA  Kenichi TAKEDA  Kang Wook LEE  Takafumi FUKUSHIMA  Mitsumasa KOYANAGI  
Summary | Full Text(in Japanese):PDF (1.8MB) >>Buy this Article

pp.344-351  PAPER
PDN Characteristics of 3D-SiP with a 4,096 bits Wide-Bus Structure
Atsushi SAKAI  Shigeru YAMADA  Takashi KARIYA  Haruya FUJITA  Hiroki TAKATANI  Yosuke TANAKA  Yoshiaki OIZONO  Yoshitaka NABESHIMA  Toshio SUDO  
Summary | Full Text(in Japanese):PDF (2.9MB) >>Buy this Article

pp.352-360  PAPER
Evaluation and Improvement of the Accuracy of Nonlinear Finite Element Analysis for a 3D SIC Package Using the Thermal Strain Measurement with SEM and DICM
Masatoshi OKA  Toru IKEDA  Noriyuki MIYAZAKI  Hiroyuki TANAKA  Takuya HATAO  Keiji MATSUMOTO  Sayuri KOHARA  Hiromitsu ORII  Fumiaki YAMADA  Morihiro KADA  
Summary | Full Text(in Japanese):PDF (3.2MB) >>Buy this Article

pp.361-370  PAPER
Electrical Testable Design for Open Defects at Logic Signal Lines between Dies in 3D ICs
Masaki HASHIZUME  Tomoaki KONISHI  Hiroyuki YOTSUYANAGI  
Summary | Full Text(in Japanese):PDF (2.5MB) >>Buy this Article

pp.371-378  PAPER
Superfine CMOS Image Sensor Module with Through-Silicon Via
Hideyuki WADA  Satoshi HIDA  Takeshi SEGI  Kenichi NAKATATE  Sayaka HIRAFUNE  Tatsuo SUEMASU  
Summary | Full Text(in Japanese):PDF (2.4MB) >>Buy this Article

pp.379-386  PAPER
Highly Reliable Chip to Chip Wiring Technology by Using Barrier Material with High Anti-Corrosion Property for 3D/2.5D-IC
Tsuyoshi KANKI  Junya IKEDA  Shoichi SUDA  Yasushi KOBAYASHI  Yoshihiro NAKATA  Tomoji NAKAMURA  
Summary | Full Text(in Japanese):PDF (2.2MB) >>Buy this Article

pp.387-392  PAPER
Relationship between Adhesion and Interface Behavior of Barrier Layer/Cu
Satoko ABE  Teruhisa BABA  Kenichi UEOKA  Yohei TAKAHASHI  Koji YONEDA  Jiping YE  
Summary | Full Text(in Japanese):PDF (1MB) >>Buy this Article

pp.393-399  PAPER
Reliability Evaluation in Flip-Chip Interconnection between Cu-pillar and Sn-Bi Solder Alloy System
Kozo SHIMIZU  Seiki SAKUYAMA  Kei MURAYAMA  Takashi KURIHARA  Mitsutoshi HIGASHI  
Summary | Full Text(in Japanese):PDF (2MB) >>Buy this Article

pp.400-408  PAPER
Micro-Texture Dependence of the Strength of Electroplated Copper Thin Film Used for Advanced 3D Electric Packages
Fumiaki ENDO  Ryosuke FURUYA  Ken SUZUKI  Hideo MIURA  
Summary | Full Text(in Japanese):PDF (1.7MB) >>Buy this Article

pp.409-418  PAPER
An Evaluating Method for Fundamental Dynamical Parameters of Objects on a Printed Circuit Board
Shin-ichi WADA  Koichiro SAWA  
Summary | Full Text(in Japanese):PDF (3.3MB) >>Buy this Article

pp.419-426  PAPER
Transient Heat Conduction Simulation of the Microprocessor Which Incorporates Power Limit Feature
Koji NISHI  Tomoyuki HATAKEYAMA  Masaru ISHIZUKA  
Summary | Full Text(in Japanese):PDF (809.3KB) >>Buy this Article

pp.427-435  PAPER
Prediction of Cooling Performance of a Small Axial Cooling Fan by Using Flow and Thermal Network Analysis
Takashi FUKUE  Tomoyuki HATAKEYAMA  Masaru ISHIZUKA  Koichi HIROSE  Katsuhiro KOIZUMI  
Summary | Full Text(in Japanese):PDF (2.9MB) >>Buy this Article

pp.436-443  PAPER
Power Supply Noise Suppression by Chip-Package-Board Co-design
Ryota KOBAYASHI  Hiroki OTSUKA  Genki KUBO  Sho KIYOSHIGE  Wataru ICHIMURA  Masahiro TERASAKI  Toshio SUDO  
Summary | Full Text(in Japanese):PDF (2.4MB) >>Buy this Article

pp.444-449  PAPER
Evaluation of Prototype No-Polish Multifiber Connector for Optical Interconnection
Tsuyoshi AOKI  Hidenobu MURANAKA  Shigenori AOKI  Katsuki SUEMATSU  Mitsuhiro IWAYA  Masato SHIINO  
Summary | Full Text(in Japanese):PDF (1.3MB) >>Buy this Article

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