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IEICE TRANSACTIONS on Electronics
0.48 1.3
Volume E82-C No.9  (Publication Date:1999/09/25)
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Special Issue on Integrated Electronics and New System Paradigms

pp.1597-1598  FOREWORD
FOREWORD
Tatsuo HIGUCHI  
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pp.1599-1606  PAPER-Quantum Devices and Circuits
A Compact Model for the Current-Voltage Characteristics of a Single Electron Transistor in the Resonant Transport Mode
Kenji NATORI  Nobuyuki SANO  
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pp.1607-1614  PAPER-Quantum Devices and Circuits
Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit
Masamichi AKAZAWA  Kentarou KANAAMI  Takashi YAMADA  Yoshihito AMEMIYA  
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pp.1615-1622  PAPER-Quantum Devices and Circuits
A Multiple-Valued Hopfield Network Device Using Single-Electron Circuits
Takashi YAMADA  Yoshihito AMEMIYA  
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pp.1623-1629  PAPER-Quantum Devices and Circuits
Analog Computation Using Coupled-Quantum-Dot Spin Glass
Nan-Jian WU  Hassu LEE  Yoshihito AMEMIYA  Hitoshi YASUNAGA  
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pp.1630-1637  PAPER-Application of Resonant Tunneling Devices
Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System
Tetsuya UEMURA  Pinaki MAZUMDER  
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pp.1638-1646  PAPER-Application of Resonant Tunneling Devices
Ultra-Fast Optoelectronic Decision Circuit Using Resonant Tunneling Diodes and a Uni-Traveling-Carrier Photodiode
Kimikazu SANO  Koichi MURATA  Taiichi OTSUJI  Tomoyuki AKEYOSHI  Naofumi SHIMIZU  Masafumi YAMAMOTO  Tadao ISHIBASHI  Eiichi SANO  
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pp.1647-1654  PAPER-Non-Binary Architectures
Compact Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits
Shugang WEI  Kensuke SHIMIZU  
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pp.1655-1661  PAPER-Non-Binary Architectures
New Non-Volatile Analog Memory Circuits Using PWM Methods
Shigeo KINOSHITA  Takashi MORIE  Makoto NAGATA  Atsushi IWATA  
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pp.1662-1668  PAPER-Non-Binary Architectures
Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic
Takahiro HANYU  Michitaka KAMEYAMA  
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pp.1669-1677  PAPER-Non-Binary Architectures
A Code-Division Multiplexing Technique for Efficient Data Transmission in VLSI Systems
Yasushi YUMINAKA  Kazuhiko ITOH  Yoshisato SASAKI  Takafumi AOKI  Tatsuo HIGUCHI  
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pp.1678-1686  PAPER-Configurable Computing and Fault Tolerance
Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits
Itsuo TAKANAMI  Satoru NAKAMURA  Tadayoshi HORITA  
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pp.1687-1698  PAPER-Configurable Computing and Fault Tolerance
Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture
Takafumi AOKI  Yoshiki SAWADA  Tatsuo HIGUCHI  
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pp.1699-1706  PAPER-Processors
Single-Chip Implementation of a 32-bit Motor-Drive-Specific Microcontroller with Floating-Point Unit
Jin-Cheon KIM  Sang-Hoon LEE  Joo-Hyun LEE  Do-Young LEE  Won-Chang JUNG  Hong-June PARK  Im-Soo MOK  Hyung-Gyun KIM  Ga-Woo PARK  
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pp.1707-1714  PAPER-Processors
Fast Computational Architectures to Decrease Redundant Calculations -- Eliminating Redundant Digit Calculation and Excluding Useless Data
Makoto IMAI  Toshiyuki NOZAWA  Masanori FUJIBAYASHI  Koji KOTANI  Tadahiro OHMI  
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pp.1715-1721  PAPER-Processors
A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor
Masahiro KONDA  Tadashi SHIBATA  Tadahiro OHMI  
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pp.1722-1729  PAPER-Processors
Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory
Masanori HARIYAMA  Kazuhiro SASAKI  Michitaka KAMEYAMA  
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pp.1730-1738  PAPER-Processors
Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology
Akira NAKADA  Masahiro KONDA  Tatsuo MORIMOTO  Takemi YONEZAWA  Tadashi SHIBATA  Tadahiro OHMI  
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pp.1739-1748  PAPER-Imaging Circuits and Algorithms
Vision Chip for Very Fast Detection of Motion Vectors: Design and Implementation
Zheng LI  Kiyoharu AIZAWA  
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pp.1749-1754  PAPER-Imaging Circuits and Algorithms
A Novel Computationally Adaptive Hardware Algorithm for Video Motion Estimation
Vasily G. MOSHNYAGA  
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pp.1755-1763  PAPER-Imaging Circuits and Algorithms
On Sensor Motion Vector Estimation with Iterative Block Matching and Non-Destructive Image Sensing
Dwi HANDOKO  Shoji KAWAHITO  Yoshiaki TADOKORO  Akira MATSUZAWA  
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pp.1764-1771  PAPER-Imaging Circuits and Algorithms
A Low-Power A/D Conversion Technique Using Correlation of Moving Pictures
Shoji KAWAHITO  Junichi NAKA  Yoshiaki TADOKORO  
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pp.1772-1776  LETTER-Low-Power Circuit Technique
Low-Power Scheme of NMOS 4-Phase Dynamic Logic
Bao-Yu SONG  Makoto FURUIE  Yukihiro YOSHIDA  Takao ONOYE  Isao SHIRAKAWA  
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Regular Section

pp.1777-1779  LETTER-Integrated Electronics
A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive
Jin-Cheon KIM  Sang-Hoon LEE  Hong-June PARK  
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